Two-Stage Gray Code Counter With Redundant-Bit Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High dynamic range image sensors require increased clock frequency for higher resolution, leading to increased power consumption in counters, which is a challenge especially in low power mobile applications.
Innovation Solution
A two-stage counter with error correction is implemented, utilizing a shared Gray code generator for lower and upper bit counters, with a redundant bit to correct phase alignment issues and reduce power consumption by limiting strict signal phase alignment requirements to the lower bit counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock frequency of the counter is increased to achieve higher resolution digital image signal outputs, then the time resolution is improved, but the power consumption of the counter increases
Solution Approach 1:
The counter is divided into two independent stages: a first stage counter and a second stage counter. The first stage counter handles lower bits and the second stage counter handles upper bits. This segmentation allows each counter to operate independently at optimized frequencies, with the first stage running at higher frequency for precision and the second stage at lower frequency for power efficiency.
Solution Approach 2:
The patent implements dynamic frequency scaling where the first stage counter operates at a first clock frequency and the second stage counter operates at a second clock frequency that is lower than the first. This dynamic approach allows the system to maintain high measurement precision in the critical lower bits while reducing overall power consumption by lowering the frequency for less critical upper bits.
2Use of energy by moving object
If a two-stage counter is used to reduce power consumption, then the power consumption is reduced, but phase alignment issues arise between the two stages
Solution Approach 1:
A phase alignment circuit is introduced as an intermediary component between the first stage counter and the second stage counter. This circuit receives the clock signal for the second stage counter and adjusts its phase based on the output of the first stage counter, ensuring proper synchronization without requiring both counters to run at the same high frequency.
Solution Approach 2:
The phase alignment is established in advance through the phase alignment circuit that pre-adjusts the clock signal phase for the second stage counter. This preliminary phase adjustment ensures that when the counters operate at different frequencies, the phase relationship remains correct, preventing alignment issues before they occur.
3Measurement precision
If the clock frequency is increased for higher resolution, then the digital image signal resolution is improved, but the counter power consumption accounts for the majority of ADC power consumption
Solution Approach 1:
The ADC counter is segmented into two stages with different operating frequencies. The first stage counter operates at higher frequency to maintain resolution accuracy for lower bits, while the second stage counter operates at lower frequency for upper bits. This segmentation reduces the overall power consumption of the ADC counter while maintaining the required digital image signal resolution.
Solution Approach 2:
The patent changes the operating frequency parameter of the counter stages differently - the first stage maintains a higher frequency for precision while the second stage uses a lower frequency. This parameter differentiation allows the ADC to achieve high resolution output without the entire counter system consuming excessive power, directly addressing the majority power consumption issue.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N-M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M-L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N-M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N-M MSBs of the second output.