Gray-Code Counter Synchronization With Zero Accumulated Error
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Solution Overview
Problem
Existing counter systems in different clock domains suffer from accumulated errors and clock domain crossing issues, necessitating additional hardware and increased power consumption.
Innovation Solution
A counter system with zero accumulated error is achieved by setting multiple time count strings, including a first string greater than and a second string less than the original, and accumulating these over multiple cycles, utilizing a Gray code encoding mechanism to ensure no error accumulation, and compensating for any timing discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional hardware is introduced to mitigate accumulated error and CDC issue, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces physical hardware mechanisms with a digital/software-based solution. Instead of using additional hardware components to correct timing errors, the invention uses a counter system that operates in one clock domain and communicates with processors in other clock domains through digital signal processing. The counter module generates timing signals that are transmitted and received across clock domain boundaries using digital encoding and decoding, eliminating the need for complex hardware synchronization circuits.
Solution Approach 2:
The patent introduces an intermediary counter system that acts as a bridge between different clock domains. The counter module serves as an intermediary component that generates timing references in its own clock domain and communicates these references to processors in other clock domains through encoded signals. This intermediary approach allows asynchronous clock domains to synchronize without direct hardware coupling, reducing overall system complexity.
2Reliability
If additional hardware is introduced to mitigate accumulated error and CDC issue, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry hardware synchronization circuits with a low-power digital counter system. The counter module uses simple counting logic and digital encoding/decoding operations that consume minimal power compared to complex hardware synchronization mechanisms. By operating the counter in a single clock domain and using digital communication protocols for cross-clock-domain interaction, the system achieves reliable synchronization with significantly reduced power consumption.
3Adaptability or versatility
If counter frequency is set below 1 GHz and not a factor of 1 GHz, then adaptability is improved, but measurement precision deteriorates due to quantization errors
Solution Approach 1:
The patent implements a feedback mechanism where the counter system continuously monitors and tracks timing relationships across different clock domains. The counter module generates timing signals and receives feedback from processors about timing deviations. This feedback information is used to adjust and correct quantization errors, maintaining high measurement precision even when operating at flexible frequencies below 1 GHz that are not factors of 1 GHz.
Solution Approach 2:
The patent dynamically adjusts operational parameters to maintain precision across different frequency conditions. The counter module can change its counting rate, accumulation period, and encoding parameters based on the operating frequency and clock domain characteristics. This adaptive parameter adjustment allows the system to maintain high measurement precision regardless of the specific counter frequency being used, enabling flexible operation at frequencies below 1 GHz.
Data Source
AI summary
A method of driving a counter system with zero accumulated error includes setting a counter frequency of a counter transmitter, setting an original time count string according to the counter frequency, setting a first time count string of the counter greater than the original time count string, setting a second time count string of the counter smaller than the original time count string, and accumulating at least one first time count string and at least one second time count string over N cycles for generating a transmitter time count string. N is greater than two. A real time string generated by the original time count string over the N cycles is equal to the transmitter time count string.