Gray-Code Digital Delay Line for Precise Clock Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital controlled delay lines (DCDLs) in integrated circuits face challenges in achieving precise delay-time adjustments with fine granularity due to the need for a large number of delay cells, which increases routing area and can result in spurious outputs and interference from device-switching.
Innovation Solution
The proposed solution involves a DCDL with a controller that uses Gray code to reduce the number of control bits, and a chain of delay cells with tri-state inverters that can operate in different modes (propagation, feedback, standby, and idle) to form various propagation paths, allowing for dynamic adjustment of delay time and minimizing interference by enabling and disabling tri-state inverters accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of delay cells are used to achieve fine granularity of delay-time adjustment, then the delay precision is improved, but the routing area increases and device-switching interference occurs
Solution Approach 1:
The delay line is divided into multiple delay cells, each contributing a specific delay amount. By selectively enabling or disabling individual delay cells through control signals, the total delay can be precisely adjusted in fine granularity steps without requiring all cells to be active simultaneously, thereby reducing routing area compared to a single large delay element.
Solution Approach 2:
The delay cells are dynamically controlled through enable/disable mechanisms using control signals. This allows the delay configuration to be changed on-the-fly without physical reconfiguration, achieving precise delay adjustment while minimizing the number of simultaneously active components, thus reducing routing area and switching interference.
2Measurement precision
If a large number of delay cells are used to achieve fine granularity of delay-time adjustment, then the delay precision is improved, but the device-switching interference increases
Solution Approach 1:
Control signals are prepared in advance to enable or disable specific delay cells before switching occurs. This preliminary control signal generation ensures that transitions between delay configurations are managed smoothly, reducing spurious outputs and interference caused by simultaneous switching of multiple delay cells.
Solution Approach 2:
The system uses control logic that monitors the current delay configuration and generates appropriate control signals to transition to the desired delay state. This feedback mechanism ensures that delay cells are switched in a controlled sequence rather than simultaneously, minimizing device-switching interference and spurious outputs while achieving the desired delay precision.
3Adaptability or versatility
If multiple delay cells are dynamically switched to adjust delay time, then the delay adjustability is improved, but the spurious outputs increase
Solution Approach 1:
Control signals act as intermediaries between the desired delay configuration and the actual state of delay cells. These control signals coordinate the enabling and disabling of delay cells in a controlled manner, ensuring that transitions occur without creating spurious outputs. The intermediary control logic manages the switching process to maintain signal integrity while achieving full delay adjustability.
Data Source
AI summary
Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.