Gray-Code Duty Cycle Error Counter for High-Speed Clock Correction
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Solution Overview
Problem
High clock speeds in DRAM and SDRAM applications make it challenging to align phases and set duty cycles accurately due to narrow timing windows and high error margins, leading to frequent counter updates and potential errors.
Innovation Solution
A duty cycle correction circuit that uses Gray code to encode bits in a counter, allowing only single-bit changes per adjustment, thereby reducing the likelihood of catastrophic errors and incorporating binary-to-Gray code and Gray-to-binary code converters to manage duty cycle errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high clock speeds are used to increase productivity, then processing speed improves, but timing alignment precision and error margins deteriorate
Solution Approach 1:
The patent changes the encoding parameter of the counter from binary to Gray code. This parameter change ensures that only one bit transitions at a time during counter updates, which directly addresses the timing alignment precision issue by eliminating multi-bit simultaneous transitions that cause errors at high clock speeds.
2Measurement precision
If frequent counter updates are performed to maintain accuracy, then measurement precision improves, but error introduction probability increases
Solution Approach 1:
The patent applies Gray code encoding to the counter, changing the representation parameter from binary to Gray code. This ensures that during frequent updates, only a single bit changes state at any transition, dramatically reducing the probability of errors even when updates occur frequently at high clock speeds.
3Ease of manufacture
If binary code is used in the counter, then ease of manufacture is maintained, but catastrophic errors occur during multi-bit transitions
Solution Approach 1:
The patent changes the encoding parameter from binary to Gray code while maintaining compatibility with standard digital logic circuits. The conversion between binary and Gray code can be achieved through simple logic gates, preserving ease of manufacture while eliminating the catastrophic errors that occur during multi-bit transitions in binary counters.
Data Source
AI summary
Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.