Gray Code Event Filter Without Reset for High-Frequency Counting
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Solution Overview
Problem
Conventional event filters in synchronous integrated circuits, such as those using binary up/down counters or bi-directional shift registers, face inaccuracies and power consumption issues when tracking high-frequency events due to reset times exceeding clock signal periods, leading to missed counts and lost shifts.
Innovation Solution
An event filter employing a Gray code counter and detection logic that increments and decrements through a Gray code sequence, allowing detection of specific count values without the need for resetting, thereby avoiding missed events by continuously counting and switching between count values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional binary up/down counters or bi-directional shift registers are used to track events, then the circuit can detect event occurrences, but reset times exceed clock signal periods at high frequencies leading to missed counts and lost shifts
Solution Approach 1:
The patent extracts and eliminates the reset operation from the counting circuit. By using a Gray code counter that continuously increments through its sequence without resetting, the circuit avoids the time loss associated with reset operations. The detection logic identifies specific Gray code patterns (e.g., '00' or '11') to generate output signals, and the counter seamlessly continues counting from where it left off, preventing missed counts even at high clock frequencies where reset time exceeds the clock period.
2Reliability
If reset operations are performed frequently in high-frequency event filtering, then the counter returns to initial state, but power consumption increases and inaccuracies occur due to missed events during reset
Solution Approach 1:
The Gray code counter maintains continuous operation by continuously incrementing through the Gray code sequence without interruption or reset. This continuous counting action ensures that no events are missed during the counting process, even at high frequencies. The detection logic continuously monitors the counter output for specific patterns, and when a pattern is detected, the counter seamlessly continues from its current state rather than resetting, thereby maintaining reliability while minimizing power consumption by eliminating frequent reset operations.
3Speed
If conventional counters are used at high clock frequencies, then event detection speed increases, but reset time exceeds clock period causing missed counts
Solution Approach 1:
The Gray code counter enables continuous operation at high clock frequencies by eliminating reset operations. The counter continuously increments through the Gray code sequence (00→01→11→10→00...) without interruption, allowing the circuit to keep pace with high-frequency clock signals. The detection logic continuously monitors for specific patterns, and upon detection, the counter seamlessly continues from its current state, ensuring no events are missed even when the clock period is shorter than conventional reset times.
Data Source
AI summary
A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.