Gray-Coded TDC Timestamp Latching for Low-Power ToF Histograms

The patent changes the encoding parameter of the time reference from binary code to gray code. This parameter change ensures that only one bit changes between consecutive time references, preventing multiple bits from changing simultaneously during latching operations. This resolves the incorrect latching issue while reducing the number of clock edges and associated power consumption compared to binary-coded schemes where multiple bits can change at once.

The patent implements periodic updating of the gray-coded time reference across the SPAD array, where each TDC latches the gray-coded address at specific periodic intervals. This periodic action allows the system to achieve high time resolution through the gray code's single-bit transition property without requiring continuous high-frequency clocking, thereby reducing overall power consumption while maintaining measurement precision.

The patent uses gray-coded addresses as direct copies or indices to access histogram bins in the histogram generation circuit. Instead of complex binary-to-gray conversion logic, the system generates gray codes periodically and uses them directly as addresses for histogram bin selection. This copying approach simplifies the overall system architecture while maintaining the power consumption and routing efficiency benefits of gray coding.