Gray Ripple Counter ADC for Uniform Code Sampling
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Solution Overview
Problem
Existing counter-ramp ADC architectures require synchronization of counter bits to an ADC clock, leading to high power consumption and potential errors due to asynchronous bit sampling and ripple delays, which introduce differential nonlinearity and limit maximum speed.
Innovation Solution
Implement a Gray ripple counter with a bit-specific delay circuit to synchronize counter bits, ensuring all codes have the same length and minimizing differential nonlinearity by adding a delay to the storage cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a binary ripple counter is used with synchronization to an ADC clock, then measurement precision is improved by ensuring all counter bits are sampled on the same counter code, but power consumption increases and the system becomes more complex
Solution Approach 1:
The patent uses a Gray counter that generates Gray codes as a copy of the binary counting sequence but with the property that only one bit changes between consecutive codes. This copying approach eliminates the need for synchronization while maintaining measurement accuracy, as the single-bit transition property inherently prevents sampling errors.
Solution Approach 2:
The patent changes the parameter of the counter output encoding from binary to Gray code. This parameter change transforms the counter behavior so that consecutive codes differ by only one bit, eliminating the need for synchronization and reducing power consumption while maintaining measurement precision.
2Device complexity
If a binary ripple counter is used without synchronization, then device complexity is reduced, but measurement precision deteriorates due to asynchronous bit sampling and ripple delays introducing differential nonlinearity
Solution Approach 1:
The Gray counter generates a copied version of the binary counting sequence with modified encoding. This copy has the critical property that only one bit transitions between consecutive codes, which eliminates differential nonlinearity and sampling errors without requiring complex synchronization circuits.
Solution Approach 2:
The Gray code encoding acts as an intermediary transformation of the binary count values. This intermediary representation ensures that counter bits can be sampled asynchronously without introducing errors, as the single-bit transition property guarantees that no intermediate values are present during switching.
3Productivity
If clocking frequency is increased to improve conversion speed, then productivity is improved, but measurement precision deteriorates due to smaller sample window and larger errors
Solution Approach 1:
The patent changes the encoding parameter from binary to Gray code, which fundamentally alters the counter's transition behavior. This parameter change allows the counter to operate at higher frequencies without sacrificing precision, as the single-bit transition property eliminates the differential nonlinearity that would otherwise worsen at high speeds.
4Device complexity
If a Gray counter is used without bit-specific delays, then device complexity is reduced, but manufacturing precision deteriorates due to differential nonlinearity from unequal code lengths
Solution Approach 1:
The patent applies local quality by introducing bit-specific delays only where needed in the Gray counter circuit. Each bit position receives a tailored delay to compensate for propagation differences, ensuring that all codes have equal length and maintaining manufacturing precision without requiring a completely complex delay circuit architecture.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a plurality of ADC circuits. Each ADC circuit is associated to a pixel group of a pixel array and includes a storage circuit including a plurality of storage cells. The ADC also includes a shared counter circuit having a counter control connection to apply a clock signal and a plurality of counter output connections. The shared counter circuit is configured to generate a respective counter bit in response to a counter state of the counter circuit. A respective one of the storage cells is connected to a respective one of the counter output connections for storing the respective counter bit. The shared counter circuit comprises a Gray ripple counter. The ADC further includes a delay circuit. The delay circuit is arranged on at least one of the counter output connections between the counter circuit and a corresponding storage cell.