Gray Code Counter Using Early Clock Signals to Cut Gate Delay
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Solution Overview
Problem
Existing gray code counters, particularly those based on binary counters, suffer from high gate count and increased gate delay, which degrades operational speed and increases power consumption in image sensing circuitry.
Innovation Solution
A gray code counter comprising a set of standard cells that reduces gate count by providing an early signal based on an early clock signal, allowing both rising and falling edges to be utilized, thereby improving speed and reducing the load on the clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If binary counters are used to generate gray code, then the counter can be implemented, but the gate count increases and gate delay increases, degrading operational speed
Solution Approach 1:
The counter is divided into multiple stages, with each stage processing a specific bit position. The gray code generation is segmented into individual flip-flop stages where each flip-flop handles one bit of the gray code output, reducing the complexity of any single gate while maintaining overall functionality
Solution Approach 2:
The conversion logic from binary to gray code is extracted and simplified by directly using the XOR relationship between adjacent binary bits. The gray code bits are generated by taking the XOR of the current binary bit with the previous binary bit, eliminating the need for complex combinational logic gates
2Speed
If binary counters are used to generate gray code, then the counter can be implemented, but the gate delay increases, degrading operational speed
Solution Approach 1:
The flip-flops are designed to preemptively update their states based on the current clock edge and the existing gray code value. The preliminary action is taken by preparing the next state in the flip-flop's internal logic before the clock edge arrives, reducing the critical path delay
Solution Approach 2:
Each flip-flop stage uses its own output and the outputs of previous stages to determine its next state through simple XOR operations. The circuit serves itself by using its current state to determine its next state without requiring complex external control logic, minimizing gate delay
3Productivity
If a large number of ripple counters are used in image sensing circuitry, then the counting function is achieved, but the clock is burdened by a large load and power consumption increases
Solution Approach 1:
Multiple counter functions are merged into a single gray code counter structure. The counter simultaneously generates gray code sequences and provides counting functionality for multiple purposes, reducing the total number of separate counter circuits and their associated power consumption
Solution Approach 2:
The counter operates in gray code mode rather than binary mode, changing the encoding parameter of the count sequence. This parameter change reduces the switching activity in the circuit because gray code transitions only change one bit at a time, thereby reducing dynamic power consumption
Data Source
AI summary
One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.