Two-Stage Gray Code Counter With Redundant-Bit Error Correction
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Solution Overview
Problem
High power consumption in counter circuits of image sensors, particularly due to increased clock frequency requirements for higher resolution digital image signal outputs, poses a challenge in reducing power consumption, especially in low-power mobile applications.
Innovation Solution
Implementing a multi-stage counter with a Lower Bit Counter and an Upper Bit Counter, where the Lower Bit Counter operates at a higher frequency and the Upper Bit Counter has a redundant bit for error correction, allowing for phase alignment and reduced power consumption by using Gray code generators shared across stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock frequency of the counter is increased to achieve higher resolution digital image signal outputs, then the time resolution is improved, but the power consumption of the counter increases
Solution Approach 1:
The counter is divided into two independent stages: a first stage counter and a second stage counter. The first stage counter operates at a higher clock frequency to provide fine time resolution, while the second stage counter operates at a lower clock frequency to reduce power consumption. This segmentation allows the system to achieve high overall resolution without requiring the entire counter to operate at high frequency, thus resolving the contradiction between time resolution and power consumption.
2Use of energy by moving object
If a multi-stage counter is used to reduce power consumption, then the power consumption is reduced, but phase alignment issues arise between stages
Solution Approach 1:
A phase alignment circuit is introduced as an intermediary component between the first stage counter and the second stage counter. This circuit receives the clock signal for the second stage counter and adjusts its phase based on the output of the first stage counter, ensuring proper synchronization. By using this dedicated phase alignment mechanism, the system achieves reliable multi-stage operation without excessive complexity, resolving the contradiction between power reduction and phase alignment requirements.
3Measurement precision
If the number of bits in the counter is increased to achieve higher resolution, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The high-resolution counter is segmented into two stages with different bit widths and operating frequencies. The first stage counter handles the least significant bits and operates at high frequency, while the second stage counter handles the most significant bits and operates at low frequency. This segmentation allows the system to achieve high overall resolution (large number of bits) without requiring all bits to be updated at high frequency, thus reducing power consumption while maintaining measurement precision.
Data Source
AI summary
An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M-L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.