Gray Code Counter with Pre-Ready Cell for Lower Gate Delay
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Solution Overview
Problem
Existing gray code counters, particularly those based on binary counters, face issues with high gate count, increased gate delay, and power consumption, which degrade operational speed and increase the load on clocks in image sensing circuitry.
Innovation Solution
A gray code counter design utilizing a set of standard cells with a pre-ready cell that provides an early signal based on an early clock signal, reducing gate count and enabling faster operation by utilizing both rising and falling edges of the clock, thereby improving speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gray code counter is generated from binary counters, then gray code functionality is achieved, but gate count increases and gate delay increases
Solution Approach 1:
The counter is divided into multiple independent bit cells, each handling a specific bit position. Each bit cell is further segmented into standard cells that can be independently optimized. This segmentation allows the gray code counter to achieve functionality with reduced gate count by eliminating redundant logic gates between binary and gray code conversion.
Solution Approach 2:
Instead of converting from binary code to gray code through additional gates, the invention inverts the approach by directly generating gray code outputs from the counter state using XOR operations at the output stage only. This eliminates the need for complex combinatorial logic gates throughout the counter structure.
2Adaptability or versatility
If additional gates are used to transfer from binary code to gray code, then gray code is generated, but gate delay increases and operational speed degrades
Solution Approach 1:
The gray code conversion function is extracted from the internal structure of the counter and placed only at the output stage. The counter itself operates in binary mode with minimal logic, and the gray code conversion is performed separately using simple XOR gates on the final output, thereby minimizing gate delay in the critical counting path.
Solution Approach 2:
The counter state is prepared in binary form, and the gray code conversion is performed as a preliminary step before output. By pre-computing the gray code bits using XOR operations on the binary state bits, the conversion is accomplished with minimal delay without affecting the counting speed.
3Productivity
If a large number of ripple counters are used in image sensing circuitry, then counting capability is achieved, but clock load increases and power consumption increases
Solution Approach 1:
Multiple counter functions are merged into a single gray code counter structure. The counter can simultaneously handle multiple counting operations and provide gray code outputs for multiple channels, thereby reducing the total number of separate counter circuits needed in image sensing circuitry and reducing overall power consumption.
Solution Approach 2:
The counter uses gray code representation instead of binary representation, which changes the state transition parameters. In gray code, only one bit changes between consecutive states, reducing the number of simultaneous switching events and thereby reducing dynamic power consumption compared to binary ripple counters where multiple bits may change simultaneously.
Data Source
AI summary
One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.