Gray Counter Clock Circuit With Glitch Shielding for ADC Timing

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Solution Overview

Problem

High-frequency clock signals used in image sensor circuits often result in a glitch at the output of gray counters, leading to ADC malfunction and missing code due to an uneven duty cycle.

Innovation Solution

A clock generating circuit that incorporates a gray counter and a shielding circuit, specifically a D-latch circuit, to analyze and eliminate glitches in the clock signal, ensuring a 50%-50% duty cycle and preventing ADC malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a gray counter is used to divide the clock signal to improve duty cycle, then the duty cycle is improved, but glitches are introduced in the output signal

Engineering Contradiction:

Improveduty cycleVSAvoidglitches

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A shielding circuit is introduced as an intermediary component between the gray counter and the ADC. This shielding circuit captures the clock signal and the first output signal from the gray counter, then generates a second output signal that combines these inputs to produce a glitch-free clock signal with proper duty cycle for the ADC.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The clock signal generation is divided into separate functional stages: the gray counter stage for duty cycle correction, and the shielding circuit stage for glitch elimination. This segmentation allows each stage to perform its specific function optimally without interfering with the other.

Inventive Principle:

Principle #1Segmentation

2Productivity

If the clock frequency is increased to improve ADC performance, then ADC performance is improved, but the duty cycle becomes uneven causing missing code

Engineering Contradiction:

ImproveADC performanceVSAvoidduty cycle

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The shielding circuit acts as an intermediary that receives both the high-frequency clock signal and the gray counter output, then synthesizes a clean clock signal with proper duty cycle that maintains high-frequency operation while eliminating duty cycle distortion.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If the gray counter operates at high frequency to maintain clock speed, then clock speed is maintained, but glitches appear causing ADC malfunction

Engineering Contradiction:

Improveclock speedVSAvoidADC reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The shielding circuit serves as a protective intermediary that filters out glitches from the high-frequency gray counter output while preserving the clock speed, thereby protecting the ADC from malfunction.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The shielding circuit uses the relationship between the clock signal and the gray counter output signal to convert the potentially harmful glitch-containing signal into a beneficial glitch-free clock signal by capturing both signals and combining them appropriately.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12222748B2Clock generating circuit

Publication Date: 2025.02.11 HIMAX IMAGING LIMITED

AI summary

A clock generating circuit includes an input terminal, configured to receive a clock signal; an output terminal, configured to output an output signal; a gray counter circuit, coupled to the input terminal, and configured to divide the clock signal to produce a first output signal; and a shielding circuit, coupled to the input terminal, the gray counter circuit and the output terminal, and configured to shield a glitch in the first output signal to generate the output signal according to the clock signal.