Gray-Code Phase Accumulator for Accurate PLL Phase Measurement
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Solution Overview
Problem
Conventional Phase-Locked Loops (PLLs) face challenges in achieving high speed, accuracy, large range, low jitter, and low power simultaneously, particularly in fractional-N PLLs, due to limitations in phase accumulator design and reference clock frequency resolution.
Innovation Solution
The proposed solution involves a PLL architecture that includes a phase accumulator with a counter that changes only one bit per cycle, a Gray counter, and a delay line with a decoder, along with a calibrator to stabilize delay line steps, enabling improved phase measurement accuracy and power efficiency by reducing counter errors and optimizing phase accumulator design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional binary counter is used in the phase accumulator, then the counting function is simple, but multiple bits change simultaneously causing measurement errors and reduced accuracy
Solution Approach 1:
The counter is segmented into multiple individual flip-flops, each handling a specific bit position. This segmentation allows independent control and timing of each bit transition, preventing simultaneous multi-bit changes and the associated measurement errors while maintaining the counting function.
Solution Approach 2:
The least significant bit flip-flop is configured to change state before more significant bit flip-flops during the counting transition. This preliminary action ensures that bit transitions occur in a controlled sequence rather than simultaneously, eliminating the measurement errors caused by multi-bit simultaneous changes.
2Productivity
If the phase accumulator uses a design that captures all counter bits simultaneously, then the phase measurement is obtained in one cycle, but timing skew between bits causes errors
Solution Approach 1:
The least significant bit flip-flop transitions before more significant bits, establishing a predetermined timing sequence. This preliminary action in the LSB ensures that when the reference clock captures the counter state, the bits are stable in their final positions, eliminating timing skew errors while maintaining single-cycle measurement capability.
Solution Approach 2:
The carry output of each flip-flop is fed back to the clock input of the next more significant bit flip-flop. This feedback mechanism ensures that bit transitions occur in the correct sequential order with proper timing relationships, preventing timing skew while enabling simultaneous capture of all bits.
3Manufacturing precision
If a fractional-N PLL is used to achieve better frequency resolution, then the frequency tuning range and resolution are improved, but the phase accumulator errors and jitter increase
Solution Approach 1:
The phase accumulator is segmented into multiple flip-flops with individual carry logic, allowing precise tracking of each bit position during fractional counting. This segmentation enables accurate representation of fractional frequency values without the accumulation of timing errors that would otherwise increase jitter.
Solution Approach 2:
The carry feedback mechanism ensures that each bit position transitions at the correct time relative to other bits, maintaining synchronization even during fractional-N operation. This feedback control prevents the phase accumulator errors and jitter that typically increase when using fractional-N PLLs for improved frequency resolution.
Data Source
AI summary
A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a counter whose output sequence changes only one bit per counted controlled oscillator output cycle, such as a Gray counter. It further includes a register or latches, which sample(s) the counter output value upon receiving a reference clock pulse. The latches output value represents the measured phase. A binary encoder, such as a Gray-to-binary converter, may translate the measured phase to a binary number. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.