Gray-Code Timer Synchronization With Fault Checks for CPU Capture
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Solution Overview
Problem
Existing methods for error detection in asynchronous data transfers from a general-purpose timer to CPUs in semiconductor devices for vehicles are ineffective, as adding error detection codes to gray-coded timer count values increases Hamming distance, leading to potential capture of invalid data and incorrect timer count values.
Innovation Solution
A semiconductor device with a timer unit that converts binary count values to gray code and a processing unit that synchronizes and compares duplicated gray code data to detect faults, ensuring the difference between count values is within a predetermined threshold to accurately determine path faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an error detection code is added to the timer count value converted into gray code, then fault detection capability is improved, but the Hamming distance between adjacent codes increases causing the CPU to capture invalid data
Solution Approach 1:
The patent divides the data path into two separate channels: one for normal timer count value transfer (Gray code) and another for fault detection (binary code with error detection). This segmentation allows each channel to optimize for its specific function without interfering with the other, resolving the contradiction between fault detection and accurate data capture.
Solution Approach 2:
The patent introduces an intermediary error detection code generated from the binary timer count value, which is then compared with the received Gray code data. This intermediary mechanism enables fault detection without directly modifying the Gray code sequence, thereby maintaining the Hamming distance properties essential for valid data capture.
2Reliability
If error detection code is added to detect faults in asynchronous transfer path, then fault detection is improved, but the data transfer complexity increases
Solution Approach 1:
The patent changes the parameter representation by generating error detection codes based on the binary form of the timer count value rather than modifying the Gray code directly. This parameter change approach simplifies the overall system by leveraging the existing binary-to-Gray conversion infrastructure while adding fault detection capability through a separate comparison mechanism.
3Productivity
If the timer operates asynchronously with multiple CPUs to improve performance, then processing speed is improved, but fault detection in the transfer path becomes difficult
Solution Approach 1:
The patent creates a copy of the timer count value in error detection code form and transmits it alongside the Gray code data to each CPU. This copying approach enables independent verification of data integrity without affecting the asynchronous operation speed, as the error detection can be performed in parallel with the main data processing.
Data Source
AI summary
A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.