Multi-Pitch Grid Layout Design for IC Area Minimization
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Solution Overview
Problem
Integrated circuit fabrication processes face challenges in achieving optimized fine pitch for multiple layout layers with different grid line pitches and widths, leading to inefficiencies in component alignment and area minimization.
Innovation Solution
The use of two layout layers with overlapping grid lines and varying line pitches and widths allows for the alignment of layout patterns with corresponding grid lines, ensuring that most components are fabricated under their optimized fine pitch, even when one set of grid lines has a wider pitch than the other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single set of grid lines is used for multiple layout layers, then alignment is simplified, but manufacturing precision deteriorates because components cannot be fabricated under their optimized fine pitch
Solution Approach 1:
The patent divides the grid line system into multiple independent sets, each optimized for specific layout layers. The first set of grid lines is dedicated to the first layout layer while the second set serves the second layout layer, allowing each layer to be fabricated at its optimized fine pitch without compromising the other layer's precision
Solution Approach 2:
The patent introduces a vertical dimension to the grid line system by creating multiple sets of grid lines at different vertical positions corresponding to different layout layers. This multi-dimensional approach enables each layer to have its own optimized grid spacing while maintaining overall alignment through the vertical stacking of grid line sets
2Manufacturing precision
If different line pitches are used for different layout layers, then manufacturing precision is improved, but alignment difficulty increases due to mismatched grid positions
Solution Approach 1:
The patent introduces alignment markers as intermediary elements that bridge the first and second sets of grid lines. These markers are positioned at intersections or corresponding locations in both grid line sets, serving as reference points that facilitate precise alignment between layers with different pitch values without requiring direct comparison of all grid lines
Solution Approach 2:
The patent allows different pitch parameters for different sets of grid lines corresponding to different layout layers. The first set of grid lines has a first pitch value optimized for the first layer, while the second set has a second pitch value optimized for the second layer, enabling each layer to be fabricated at its optimal resolution
3Difficulty of detecting and measuring
If grid lines are made wider to improve visibility, then measurement ease is improved, but manufacturing precision deteriorates due to increased line width consuming valuable space
Solution Approach 1:
The patent applies different line width qualities to different portions of the grid line system. The grid lines used for alignment references and markers are made wider to improve visibility and measurement ease, while the grid lines that define actual component locations maintain narrower widths to preserve manufacturing precision and maximize space utilization for functional components
Data Source
AI summary
A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.