Uniform Grid Metal Gate Layout With Trench Contact Cut Simplification
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors has led to challenges in maintaining mobility improvement and short channel control as device dimensions approach the 10 nanometer node, while also facing constraints in lithographic processes that affect critical dimension and spacing between features.
Innovation Solution
The implementation of a metal gate process with trench contact cuts and source or drain depopulation, using a single 'infinite' grating to generate trench contact plugs and gate cut plugs, followed by local plug removal to reconnect cut gate and contact portions, thereby simplifying the trench contact and poly cut process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate and nanowire transistors are scaled to smaller dimensions, then device density and functional unit capacity are increased, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The transistor channel is segmented into multiple nanowires arranged in a vertical stack configuration, with each nanowire providing an independent conduction path. This segmentation allows the gate to control multiple channels simultaneously, improving short channel control while maintaining high device density through vertical stacking rather than lateral scaling
2Productivity
If the number of fundamental building blocks is increased in a given region, then device capacity is improved, but constraints on lithographic processes become overwhelming
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional vertical stacking of nanowires. This dimensional change allows multiple devices to be packed into a smaller footprint area by utilizing the vertical dimension, thereby increasing device capacity without proportionally increasing lithographic process complexity
3Reliability
If trench contact and poly cut processes are performed separately with multiple steps, then device performance can be optimized, but process variation and complexity increase
Solution Approach 1:
The trench contact formation and polysilicon gate cutting processes are merged into a single unified process step. By performing both operations simultaneously using the same etch process and alignment references, the patent reduces process variation between the two operations while maintaining the ability to optimize device performance through precise control of contact and gate dimensions
Data Source
AI summary
Integrated circuit structures having uniform grid metal gate and trench contact cut with source or drain depopulation, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut with source or drain depopulation, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin, a gate electrode, and a dielectric structure in a source or drain location at an end of the vertical stack of horizontal nanowires or the fin. A dielectric sidewall spacer is between the gate electrode and the dielectric structure, and first and second dielectric cut plug structures are extending through the gate electrode, through the dielectric sidewall spacer, and through the dielectric structure.