Grid Structure Constraining Ferroelectric Domain Sizes

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Solution Overview

Problem

Ferroelectric memory cells face challenges due to variations in grain sizes and ferroelectric domain sizes across the ferroelectric material, leading to increased power consumption, reduced endurance, and bit-to-bit variations in memory arrays.

Innovation Solution

A ferroelectric memory device with a ferroelectric structure that includes a ferroelectric layer disposed within a grid structure, where the grid structure comprises sidewalls defining openings that restrict the size of ferroelectric domains, thereby enhancing uniformity and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If ferroelectric material is used in memory cells, then non-volatile storage is achieved, but variations in grain sizes and domain sizes cause increased power consumption and reduced endurance

Engineering Contradiction:

Improvepower consumptionVSAvoidendurance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies local quality by introducing a grid structure with specific geometric patterns that locally constrain the ferroelectric material. This creates uniform local environments for domain formation, ensuring consistent domain sizes and shapes across different regions of the memory cell, thereby reducing variations that lead to power consumption issues and reduced endurance

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameters of the ferroelectric material by confining it within a grid structure defined by sidewalls. This confinement alters the domain size, shape, and distribution parameters, creating more uniform ferroelectric domains that reduce power consumption and improve device reliability and endurance

Inventive Principle:

Principle #35Parameter changes

2Reliability

If ferroelectric material is used in memory cells, then non-volatile storage is achieved, but bit-to-bit variations occur across memory arrays

Engineering Contradiction:

ImproveuniformityVSAvoidbit-to-bit variation

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The grid structure creates identical local environments for each memory cell in the array, with standardized sidewall patterns that enforce uniform domain formation. This local standardization ensures consistent electrical characteristics across all bits, reducing bit-to-bit variations and improving manufacturing precision

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The grid structure segments the ferroelectric material into discrete, uniformly-sized regions defined by the sidewalls. This segmentation ensures that each memory cell contains ferroelectric domains of controlled size and shape, leading to more uniform electrical properties across the entire memory array

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12245435B2Grid structure to reduce domain size in ferroelectric memory device

Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip including a first dielectric layer over a substrate. A first conductive structure overlies the first dielectric layer. A data storage structure is disposed between the first dielectric layer and the first conductive structure. The data storage structure comprises a data storage layer and a grid structure. The grid structure comprises a plurality of opposing sidewalls spaced across a width of the first conductive structure. The data storage layer is disposed along the plurality of opposing sidewalls. The data storage layer comprises a first material and the grid structure comprises a second material different from the first material.