Groove-Filled Chip Package for Higher Conduction and Yield
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Solution Overview
Problem
Conventional chip packages face challenges in achieving high conductive efficiency and yield rate, leading to reduced reliability and consumer trust.
Innovation Solution
A chip package design incorporating highly concentrated silver or copper paste-filled grooves between dielectric layers, with die-pad bumps for enhanced electrical connection and protection, improving conductive efficiency and yield rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip package structures are used, then manufacturing simplicity is maintained, but electrical conduction efficiency deteriorates
Solution Approach 1:
The patent transitions from planar 2D conductive traces to 3D vertical grooves filled with conductive paste, creating conductive pathways that extend through multiple dielectric layers. This dimensional change enables direct electrical connection between die pads and bonding pads while improving conduction efficiency without excessive complexity increase
Solution Approach 2:
The patent uses composite conductive paste materials containing silver or copper particles suspended in a polymer matrix. This composite structure provides both mechanical adhesion to fill the grooves and high electrical conductivity, resolving the contradiction between structural integrity and conduction efficiency
2Productivity
If conventional chip package structures are used, then manufacturing process simplicity is maintained, but product yield rate deteriorates
Solution Approach 1:
The patent forms protective die-pad bumps before subsequent manufacturing steps. This preliminary protective action prevents damage to die pads during later processing, thereby improving yield rate without significantly complicating the overall manufacturing flow
Solution Approach 2:
The patent modifies material parameters by using highly conductive paste with specific particle concentrations and viscosities that enable reliable filling of grooves through standard dispensing processes. This parameter optimization achieves high yield rates without requiring complex manufacturing equipment
3Reliability
If conventional chip package structures are used, then structural simplicity is maintained, but reliability deteriorates
Solution Approach 1:
The patent embeds conductive paste within grooves of dielectric layers, creating a nested structure where conductive elements are housed within insulating matrices. This nesting provides both mechanical protection and electrical isolation, improving reliability while maintaining reasonable structural complexity
Solution Approach 2:
The patent introduces dielectric layers as intermediary materials between the chip substrate and external bonding pads. These dielectric layers with embedded conductive grooves act as mediators that provide both electrical connection pathways and mechanical/chemical isolation, enhancing reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances electrical conduction efficiency and product yield rate, addressing the reliability issues of conventional chip packages.
Implementation Method 1
The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit
Data Source
AI summary
A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.