Groove Hard Mask Patterning for Source/Drain Local Interconnects
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in achieving design flexibility and reliability for local interconnects, particularly in minimizing the size of standard cells and ensuring accurate connection between source/drain regions and metal wiring layers.
Innovation Solution
The process involves forming a conductive source/drain contact layer on the source/drain epitaxial region, creating a groove pattern in a hard mask layer to pattern the source/drain contact layers, and filling these patterns with a conductive material to enhance electrical connectivity and reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If local interconnect structures are introduced to enhance design flexibility and minimize standard cell size, then device size and design flexibility are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming mandrels, depositing first hard mask layer, forming first hard mask patterns, depositing second hard mask layer, forming second hard mask patterns, and selective removal. This segmentation of the complex local interconnect fabrication into manageable discrete steps reduces manufacturing complexity while maintaining design flexibility
Solution Approach 2:
Mandrels are formed in advance before the actual local interconnect patterns are created. The first and second hard mask layers are deposited and patterned sequentially as preliminary steps that prepare the structure for final local interconnect formation, making the overall process more controllable and less complex
2Manufacturing precision
If multiple patterning steps are used to achieve precise local interconnect patterns, then manufacturing precision is improved, but production time and process complexity increase
Solution Approach 1:
Mandrels are formed as preliminary structures that guide subsequent patterning steps. The first hard mask layer is deposited and patterned before the second hard mask layer, creating a hierarchical patterning approach that achieves high precision while organizing steps efficiently to minimize overall production time
Solution Approach 2:
The patent uses vertical layering with multiple hard mask layers deposited at different heights and patterned at different stages. This three-dimensional approach to patterning allows precise local interconnect formation by controlling which layers are etched at each step, achieving high precision without requiring excessive sequential processing time
3Measurement precision
If selective removal of hard mask layers is employed to form accurate connections, then connection accuracy is improved, but process difficulty and manufacturing complexity increase
Solution Approach 1:
The first and second hard mask layers act as intermediary protective layers that are selectively removed to expose specific regions. These intermediary layers mediate between the mandrel structures and the final local interconnect patterns, enabling accurate connections by protecting areas that should not be etched while allowing etching in target regions
Solution Approach 2:
The hard mask removal process is segmented into selective steps where the first hard mask layer is removed in specific regions, followed by selective removal of the second hard mask layer in different regions. This segmented selective removal approach achieves high connection accuracy by controlling exactly which areas are exposed at each etching step, making the complex selective process more manageable
Data Source
AI summary
In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.