Groove MOS Transistor for Short-Channel Effect Control
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Solution Overview
Problem
Existing MOS transistors face challenges in reducing short-channel effects due to limitations in gate insulation layer thickness and complexity in creating shallow junction source and drain structures, leading to increased leakage current and malfunctioning.
Innovation Solution
A MOS transistor design where a gate stack is formed in a groove lower than the source and drain areas, with a lightly doped drain and halo implantation structure, and a metal silicide layer, reducing short-channel effects while simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is scaled down to increase device speed, then the device can work faster, but short-channel effects arise leading to increased leakage current and malfunctioning
Solution Approach 1:
The patent introduces a vertical dimension by forming a groove in the substrate and placing the gate stack within it, creating a three-dimensional structure. This dimensional change allows the gate to extend deeper into the channel region, improving electrostatic control over the shortened channel and suppressing short-channel effects while maintaining high device speed
2Reliability
If the gate insulation layer thickness is decreased to reduce short-channel effects, then short-channel effects are reduced, but leakage current and breakdown increase
Solution Approach 1:
Instead of further thinning the gate insulation layer, the patent uses a vertical groove structure to extend the gate's有效控制 region downward. This dimensional approach provides additional electrostatic control without increasing electric field stress on the insulation layer, avoiding leakage and breakdown issues
Solution Approach 2:
The patent changes the geometric parameters of the gate structure by forming it within a groove of specific depth and width ratios. This parameter optimization allows the gate to exert stronger control over the channel while maintaining safe electric field levels in the insulation layer
3Reliability
If an epitaxial technique is used to produce an elevated source and drain structure to reduce short-channel effects, then short-channel effects are reduced, but the process becomes complex, costly, and difficult to control
Solution Approach 1:
Instead of elevating the source and drain structures above the gate (as in epitaxial approaches), the patent inverts the approach by placing the gate stack within a groove, making the gate lower than the source and drain regions. This achieves the same electrostatic control benefit with simpler planar fabrication processes
Solution Approach 2:
The patent uses standard semiconductor fabrication techniques (photolithography, etching, deposition, ion implantation) to create the groove and gate stack, copying proven process flows rather than requiring new epitaxial equipment and processes, thereby reducing complexity and cost
Data Source
AI summary
The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas.