Groove Word Line Structure for Dense, Low-Resistivity Memory Cells
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Solution Overview
Problem
The challenge of increasing integration density in semiconductor devices is hindered by the need for novel and expensive exposure technologies, making it difficult to reduce linewidths effectively.
Innovation Solution
A semiconductor device design featuring a substrate with grooves, a gate insulating layer, and conductive patterns with specific grain dimensions and impurity contents, along with a word line capping pattern, is fabricated using a method that includes conformal deposition and thermal treatment to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If linewidths of patterns are reduced to increase integration density, then integration density is improved, but novel and expensive exposure technologies are needed
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional groove-based transistors. By forming transistors within grooves etched into the substrate, the device achieves vertical stacking and spatial efficiency, increasing integration density without requiring further reduction of lithographic linewidths. This dimensional transition allows continued scaling using existing exposure technologies.
Solution Approach 2:
The patent segments the transistor structure into distinct components formed in the groove: gate insulating layer, first conductive pattern (word line), second conductive pattern, and capping pattern. This segmentation allows each component to be optimized independently and formed using standard semiconductor fabrication processes, avoiding the need for novel exposure technologies while achieving high integration density.
2Reliability
If grain size of conductive material is increased to reduce resistivity, then electrical conductivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different grain size requirements to different regions of the conductive pattern. The first conductive pattern (word line) adjacent to the gate insulating layer has larger grain sizes (10-100 nm) to reduce contact resistivity and improve electrical reliability. This local optimization of grain structure allows high conductivity without requiring uniform large-grain formation throughout the entire device, thereby managing manufacturing precision requirements effectively.
3Reliability
If impurity content is increased in conductive portions to reduce resistivity, then electrical conductivity is improved, but interface traps increase
Solution Approach 1:
The patent implements spatially differentiated impurity distribution: the first conductive pattern (word line) contains higher impurity content to reduce its intrinsic resistivity and improve electrical conductivity, while the gate insulating layer maintains lower impurity content to minimize interface traps at the critical gate insulator/conductive pattern interface. This local quality differentiation allows simultaneous optimization of both electrical conductivity and interface quality.
Solution Approach 2:
The gate insulating layer acts as an intermediary barrier between the high-impurity first conductive pattern and the substrate. This intermediate layer with controlled (lower) impurity content prevents impurity diffusion and reduces interface trap formation at critical interfaces, while still allowing the adjacent conductive portions to maintain high impurity content for low resistivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability and operation speed of semiconductor devices by reducing resistivity, interface traps, and power consumption, while maintaining high integration density.
Implementation Method 1
a method that includes conformal deposition and thermal treatment to enhance reliability
Data Source
AI summary
Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.