Grooved Stacked Ceramic Capacitor Package for EOS and Crack Control
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Solution Overview
Problem
Existing stacked ceramic capacitors face issues with noise, vibration, cracks due to piezoelectric properties, and resistance to inrush current and Electrostatic Overvoltage (EOS), leading to circuit failure and increased volume and cost in electric vehicle applications, especially with non-uniform capacitance values across wide voltage ranges.
Innovation Solution
A stacked ceramic capacitor package with a composite structure featuring terminal structures with grooves and protrusions to minimize bonding area, incorporating a protection element like a varistor or TVS diode, and using materials like X7T and PLZT for stable capacitance across a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stacked ceramic capacitors are connected in series to increase withstand voltage, then EOS resistance is improved, but device complexity and volume increase
Solution Approach 1:
The patent combines multiple ceramic capacitor elements with different voltage ratings into a single integrated package structure. The package includes a first ceramic capacitor element with a first voltage rating and a second ceramic capacitor element with a second voltage rating, both connected to common first and second external terminals. This merging approach provides series connection functionality for increased EOS resistance while maintaining a single compact device rather than multiple separate components.
2Quantity of substance
If stacked ceramic capacitors are used for high capacitance applications, then energy storage is improved, but capacitance uniformity across wide voltage range deteriorates
Solution Approach 1:
The patent applies different ceramic capacitor elements with different voltage ratings to different parts of the overall capacitance requirement. The first ceramic capacitor element has a first voltage rating and the second ceramic capacitor element has a second voltage rating, where each element is optimized for its specific voltage range. This local quality approach ensures that each capacitor element operates within its optimal voltage range, maintaining capacitance uniformity across the wide overall voltage range from 12V to 800V.
3Reliability
If terminal structures are enlarged to improve electrical connection, then electrical conductivity is improved, but mechanical stress on ceramic capacitor increases
Solution Approach 1:
The patent segments the terminal connection structure by providing distinct first and second terminal structures that are selectively connected to different ceramic capacitor elements. The first terminal structure is connected to the first external terminal and the second terminal structure is connected to the second external terminal. This segmentation allows for optimized electrical connection paths while distributing mechanical stresses across multiple connection points rather than concentrating them in a single large terminal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The package prevents noise and cracks, provides EOS protection, and maintains stable capacitance characteristics, reducing circuit volume and cost while supporting high-capacity applications in electric vehicles.
Implementation Method 1
a stacked ceramic capacitor package for an electronic device to prevent noise, vibration, and cracks due to piezoelectric properties
Implementation Method 2
a circuit protection method of separately adding an EOS protection device such as a varistor or a TVS diode to a front end portion of a circuit
Implementation Method 3
a stacked ceramic capacitor having capacitance characteristics with a low rate of change
Data Source
AI summary
Provided is a stacked ceramic capacitor package, for an electronic device, preventing noise, vibration and cracks due to piezoelectric properties. The ceramic capacitor package for an electronic device comprises: stacked ceramic capacitors; a first terminal structure connected to a first side surface of the stacked ceramic capacitors; and a second terminal structure connected to a second side surface of the stacked ceramic capacitors and disposed so as to face the first terminal structure with the stacked ceramic capacitors therebetween. The first terminal structure has a first groove defined in an area coming into contact with the first side surface of the stacked ceramic capacitors. The horizontal length of the first groove is 30% to 50% of the horizontal length of the stacked ceramic capacitors.