Grooved Semiconductor Chip Stacking for Void-Free Resin Sealing
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Solution Overview
Problem
In semiconductor devices with stacked chips and a controller chip sealed using an insulating sealing member, the space filling by the sealing member is often insufficient, leading to potential voids that can cause issues during reflow processes.
Innovation Solution
The semiconductor device design includes a groove on the first semiconductor chip that divides its surface into two portions, with bonding layers between these portions and the wiring substrate, and a second semiconductor chip placed inside the groove, using a die attach film and sealing resin to ensure complete filling and sealing of the space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating sealing member is used to seal the controller chip and stacked chips, then the sealing function is provided, but the space filling is insufficient leading to voids
Solution Approach 1:
The first semiconductor chip surface is divided into multiple regions by grooves, creating segmented bonding areas. This segmentation allows the sealing resin to be distributed and bonded in discrete zones, improving space filling and eliminating voids while maintaining sealing reliability.
Solution Approach 2:
Grooves are formed on the first semiconductor chip surface before bonding occurs. This preliminary action creates predetermined bonding regions that guide the sealing resin placement, ensuring complete space filling and preventing void formation during the subsequent bonding and sealing processes.
2Manufacturing precision
If a groove is formed on the first semiconductor chip to improve sealing filling, then the space filling is improved, but the device structure becomes more complex
Solution Approach 1:
The groove structure segments the chip surface into distinct bonding regions, which simplifies the bonding process by providing clear boundaries for sealing resin placement. While adding grooves increases structural elements, it organizes the bonding process and improves manufacturing precision.
Solution Approach 2:
The grooves create local variations in surface topology, concentrating bonding functionality in specific regions. This local quality approach allows the sealing resin to be precisely positioned where needed, improving space filling without requiring complex modifications to the entire chip structure.
3Reliability
If multiple bonding layers are used to fill the space completely, then the void prevention is improved, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple bonding layers are applied to different segmented regions of the chip surface defined by grooves. Each bonding layer targets a specific region, ensuring complete space filling without requiring complex multi-step processes. The segmentation guides the bonding process and simplifies quality control.
Solution Approach 2:
The groove pattern is established before bonding, creating a template that guides subsequent bonding layer application. This preliminary structuring allows multiple bonding layers to be applied systematically to different regions, improving void prevention while maintaining process manageability.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a wiring substrate and a first semiconductor chip. The first semiconductor chip has a first surface facing the wiring substrate. The first surface has a groove. The groove extends across the first surface and divides the first surface into a first portion and a second portion. A first bonding layer is between the first portion of the first surface and the wiring substrate. A second bonding layer is between the second portion of the first surface and the wiring substrate. A second semiconductor chip is on the wiring substrate. The second semiconductor chip has a portion inside the groove of the first semiconductor chip. A third bonding layer is between the bottom of the groove and a second surface of the second semiconductor chip.