Grooved Contact Power MOS Transistor Interconnect
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Solution Overview
Problem
Conventional power MOSFET manufacturing processes require multiple metal layers and complex via processing steps, leading to increased costs and reduced silicon area efficiency due to the need for additional process steps and potential contamination of semiconductor layers.
Innovation Solution
The use of grooved contact structures, where contact grooves are formed within a dielectric layer to connect active regions directly with metal, eliminating the need for additional metal layers and via processing steps, allowing for tighter pitch and cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metal layers and via processing steps are used to interconnect source and drain areas, then electrical connection reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention extracts and eliminates the via processing steps and additional metal layers from the conventional interconnection process. By using grooved contacts that extend through the dielectric layer, the patent removes the need for separate via formation and filling operations, thereby reducing manufacturing complexity while maintaining electrical connection reliability
Solution Approach 2:
The invention merges the contact formation and metal interconnection steps into a single integrated process. The grooved contacts are formed and filled with metal in one continuous operation, eliminating the need for separate via processing and reducing the total number of manufacturing steps required to achieve reliable electrical connections
2Reliability
If additional metal layers are deposited to ensure adequate metal wire size for lead frame connection, then electrical conductivity is improved, but silicon area efficiency decreases
Solution Approach 1:
The invention transitions from a planar metal layer approach to a three-dimensional grooved contact structure. By etching grooves into the dielectric layer and filling them with metal, the patent achieves adequate metal wire size and electrical conductivity through vertical dimension exploitation rather than requiring additional horizontal metal layers, thereby improving silicon area efficiency
Solution Approach 2:
The invention changes the geometric parameters of the contact structure by forming grooves with specific depth and width dimensions. This dimensional parameter change allows the metal interconnection to achieve the required conductivity within the available silicon area, eliminating the need for additional metal layers that would reduce area efficiency
3Ease of manufacture
If metal is deposited directly on semiconductor die surface, then manufacturing process is simplified, but semiconductor layers become contaminated and device becomes inoperable
Solution Approach 1:
The invention introduces a dielectric layer as an intermediary between the semiconductor surface and the metal deposition. This dielectric layer serves as a protective barrier that prevents metal contamination of the semiconductor layers while still allowing electrical connection through the grooved contacts that extend through the dielectric to the source and drain areas
4Reliability
If via processing steps are used to create contact holes for metal deposition, then electrical connection is achieved, but manufacturing cost and process time increase
Solution Approach 1:
The invention performs the contact groove formation as a preliminary action that integrates with the existing dielectric layer deposition process. By forming the grooved contacts during the dielectric layer formation stage rather than as a separate subsequent via processing step, the patent reduces manufacturing process time while ensuring proper electrical connection pathways are established before metal deposition
Data Source
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AI summary
A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.