Grooved Dielectric Electronic Package for Warpage-Tolerant Bonding
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Solution Overview
Problem
Conventional 3D chip stacking technologies face high costs and reliability issues due to thermal stress-induced warpage, caused by mismatched coefficients of thermal expansion among packaging materials, leading to poor electrical connections and manufacturing defects.
Innovation Solution
The design incorporates a dielectric layer with grooves that accommodate conductors and protection layers, preventing voids and ensuring proper alignment, and includes conductive components and vias to maintain electrical connections despite potential warpage, using a non-conductive film for protection and forming conductive pillars through the layer for secure bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D chip stacking with TSI is used, then electrical connections can be established, but thermal stress-induced warpage occurs due to CTE mismatch among packaging materials
Solution Approach 1:
The patent introduces a compliance layer with specific mechanical properties (younger modulus than surrounding packaging materials) to accommodate thermal expansion differences. This parameter change in material stiffness allows the structure to absorb thermal stress through controlled deformation rather than rigid resistance, preventing warpage while maintaining electrical connections.
Solution Approach 2:
The compliance layer acts as an intermediary between components with different CTE values. This intermediate layer absorbs and distributes thermal stress, mediating the mechanical incompatibility between the TSI, packaging substrate, and encapsulant, thereby preventing direct stress transmission that causes warpage and connection failure.
2Manufacturing precision
If rigid packaging structure is used to maintain alignment, then manufacturing precision can be achieved, but thermal stress causes warpage and connection failure
Solution Approach 1:
The compliance layer's specific mechanical parameter (younger modulus) enables it to deform elastically under thermal stress while maintaining sufficient rigidity during manufacturing processes. This parameter optimization allows the structure to be precise during assembly but flexible during thermal cycling, resolving the contradiction between manufacturing precision and operational reliability.
Data Source
AI summary
An electronic package is provided and includes a protection layer formed on the electronic structure having a plurality of conductors to cover the plurality of conductors, a dielectric layer having a plurality of grooves to enable the electronic structure to be bonded onto one side of the dielectric layer with the protection layer thereon such that each of the plurality of conductors is correspondingly accommodated in each of the plurality of grooves, and a plurality of conductive components disposed on another side of the dielectric layer. Accordingly, the design of the grooves is used to correspond to the high and low surfaces of the electronic structure such that the problem of poor manufacturing process can be avoided.