Grooved Gate Electrode Depth Shielding for Semiconductor Reliability
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Solution Overview
Problem
Conventional semiconductor devices with gate electrodes in groove portions require additional oxide films to prevent dielectric strength reduction, complicating the fabrication process.
Innovation Solution
The semiconductor device features gate electrodes with upper ends positioned deeper than the impurity introduction range, eliminating the need for additional insulating films and simplifying the fabrication process by preventing impurity implantation into the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional oxide films are formed to prevent dielectric strength reduction, then the gate insulating film is protected from impurity damage, but the fabrication process becomes complicated
Solution Approach 1:
The invention extracts and eliminates the additional oxide films (screen oxide film and upper oxide film) from the conventional structure. By positioning the gate electrode upper ends deeper than the impurity introduction range, the patent removes the need for these protective oxide films, simplifying the fabrication process while maintaining gate insulating film protection through the depth-based shielding approach
Solution Approach 2:
The invention transitions from a lateral protection approach (using oxide films covering the gate insulating film surface) to a depth-based protection approach. By controlling the vertical position of the gate electrode upper ends to be deeper than the impurity introduction range, protection is achieved through dimensional repositioning in the depth direction rather than through additional lateral film layers
2Reliability
If additional oxide films are formed to protect the gate insulating film, then dielectric strength is maintained, but manufacturing steps increase
Solution Approach 1:
The invention removes the screen oxide film formation step and the upper oxide film formation step from the fabrication process. By using depth-based positioning of gate electrode upper ends below the impurity introduction range, the patent eliminates these manufacturing steps entirely, improving fabrication efficiency while maintaining reliability through the depth-based protection mechanism
Solution Approach 2:
The invention performs preliminary action by pre-positioning the gate electrode upper ends at a depth greater than the impurity introduction range before ion implantation occurs. This preliminary depth positioning creates inherent protection against impurity damage, eliminating the need for subsequent oxide film formation steps and improving overall manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains dielectric strength voltage without additional insulating films, simplifying the fabrication process and reducing the risk of gate insulating film damage.
Implementation Method 1
an impurity introduced from a main surface of the semiconductor substrate with respect to the insulating film in order to form the source impurity region
Data Source
AI summary
A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.