Grooved Molding Layer in 2.5D Semiconductor Packages for Warpage Control

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Solution Overview

Problem

The existing 2.5D semiconductor package products face issues with warpage due to differences in coefficients of thermal expansion between components, leading to poor solder wettability and reliability during bonding processes.

Innovation Solution

A semiconductor package design that includes a package substrate, an interposer, semiconductor devices, and a molding layer with grooves extending between the devices. The molding layer has a higher coefficient of thermal expansion than the semiconductor devices, minimizing warpage and improving solder wettability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a molded interposer is used to provide high-density interconnection in a 2.5D package, then interconnection density is improved, but warpage occurs due to difference in coefficients of thermal expansion between components, leading to poor solder wettability

Engineering Contradiction:
Improveinterconnection densityVSAvoidsolder wettability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces grooves at specific locations in the molding layer to create local structural variations. These grooves are positioned between adjacent semiconductor devices to selectively reduce thermal coupling in critical areas while maintaining overall package integrity. This local modification approach allows the molding layer to have different thermal expansion characteristics in different regions, compensating for the coefficient of thermal expansion mismatch between the interposer and semiconductor devices.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The molding layer is segmented by introducing grooves that divide the continuous molding material into distinct regions. This segmentation creates thermal isolation zones between adjacent semiconductor devices, preventing uniform thermal expansion across the entire molding layer. The grooves effectively partition the thermal stress distribution, allowing each semiconductor device to experience more uniform thermal conditions during soldering processes.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If components with different coefficients of thermal expansion are bonded together in a molded interposer, then functional integration is improved, but bending behaviors do not match in high temperature sections, causing non-wetting phenomenon

Engineering Contradiction:
Improvefunctional integrationVSAvoidbonding precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The grooves are strategically positioned between semiconductor devices to create local thermal management zones. These localized structural modifications allow different regions of the molding layer to expand and contract differently during temperature cycling, compensating for the inherent thermal expansion mismatches between components with different coefficients of thermal expansion. This maintains bonding precision in critical areas while preserving functional integration.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design enhances the reliability of the 2.5D semiconductor package by improving solder wettability and reducing thermal disconnection effects, thereby preventing thermal-coupling phenomena.

Implementation Method 1

warpage occurs due to a difference in coefficients of thermal expansion between individual components constituting the molded interposer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

improving solder wettability and reducing thermal disconnection effects, thereby preventing thermal-coupling phenomena

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12237240B2Semiconductor package and method of manufacturing semiconductor package
Publication Date: 2025.02.25 SAMSUNG ELECTRONICS CO LTD
  • US12237240B2 patent drawing
  • US12237240B2 patent drawing
  • US12237240B2 patent drawing

AI summary

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.