Grooved Oxide-Semiconductor Memory Cell for Dense Reliable Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face limitations in reducing the size of memory cells while maintaining high reliability and large memory capacity, as existing methods for miniaturization are not sufficient to achieve significant reductions in circuit area.
Innovation Solution
A memory device structure incorporating a transistor with a first oxide semiconductor, a conductor, and a second oxide semiconductor with a curvature, embedded in a groove, along with a capacitor device, utilizing indium and other elements like gallium, yttrium, or tin, to enhance channel formation and reduce impurity concentrations, thereby increasing effective channel length and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimension of the memory cell is reduced by stacking transistors three-dimensionally using silicon or oxide semiconductor, then the memory capacity increases, but the circuit area reduction is limited and reliability may deteriorate
Solution Approach 1:
The patent implements a three-dimensional stacked transistor structure where oxide semiconductor layers are stacked vertically to form multiple channels. This vertical stacking approach transitions from planar two-dimensional transistor layouts to three-dimensional structures, enabling increased memory capacity within a reduced footprint while maintaining reliable operation through controlled channel formation in each stacked layer
Solution Approach 2:
The patent employs composite material structures combining oxide semiconductor layers with conductor layers and insulator layers. The oxide semiconductor contains multiple elements including indium, gallium, zinc, and oxygen in specific ratios to optimize electrical characteristics. This composite structure enables both high capacity and reliability by leveraging the complementary properties of different materials in the stacked transistor configuration
2Quantity of substance
If the element size is miniaturized to increase memory capacity, then the circuit area decreases, but the manufacturing precision and reliability become difficult to maintain
Solution Approach 1:
The patent divides the transistor structure into multiple stacked segments, with each segment comprising an oxide semiconductor layer, conductor layers, and insulator layers. This segmentation allows each layer to be formed with controlled thickness and composition, facilitating precise manufacturing of miniaturized elements while maintaining overall device performance and reliability
Solution Approach 2:
The patent controls the atomic ratios of elements within the oxide semiconductor, specifically maintaining indium at 30-70 atomic%, gallium at 5-30 atomic%, zinc at 10-40 atomic%, and oxygen at 10-40 atomic%. By precisely controlling these compositional parameters, the patent achieves reliable manufacturing of miniaturized memory cells with consistent electrical characteristics
3Quantity of substance
If the circuit area is reduced through layout optimization, then the memory capacity increases, but further reduction in circuit area becomes difficult
Solution Approach 1:
The patent utilizes vertical stacking to extend the transistor structure into the third dimension, allowing multiple memory cells to be stacked above one another. This approach decouples memory capacity from planar circuit area, enabling continued capacity increases without proportional increases in footprint area by exploiting the vertical dimension for additional storage elements
Data Source
AI summary
A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.