Grooved Electronic Package Layout for Thin Coreless Assembly
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Solution Overview
Problem
Conventional semiconductor packages are thick due to the structure design, which includes a first package substrate with a core layer and a semiconductor chip located above it, leading to increased thickness and high fabricating costs due to the need for extensive packaging gel coverage.
Innovation Solution
A semiconductor package design featuring a groove on the circuit structure to bury the electronic element, with a cladding layer only covering the groove area, and an external connection structure stacked on the second side, utilizing coreless circuit and connection structures to reduce thickness and fabricating costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure with core layers and stacked substrates is used, then electrical connection and system integration are achieved, but the package thickness significantly increases
Solution Approach 1:
The patent transitions from a three-dimensional stacked structure to a two-dimensional planar structure by arranging circuit patterns and conductive elements on the same substrate plane. This dimensional change eliminates the need for vertical stacking, thereby reducing package thickness while maintaining electrical connection functionality through lateral routing of signals.
Solution Approach 2:
The patent extracts and removes the core layers from the package structure, retaining only the essential circuit functionality implemented directly on the substrate. By taking out the intermediate core layers and using the substrate itself as the circuit carrier, the overall package thickness is reduced while electrical connections are maintained through direct patterning on the substrate surface.
2Reliability
If packaging gel is used to encapsulate all surface areas to protect solder pillars and semiconductor chips, then structural integrity and protection are achieved, but fabricating cost increases
Solution Approach 1:
The patent extracts and removes the packaging gel entirely from the structure by eliminating the solder pillars and semiconductor chips that required encapsulation. The substrate itself serves as the protective structure, and circuit elements are directly integrated onto the substrate surface, eliminating the need for additional encapsulation materials and reducing manufacturing cost.
Solution Approach 2:
The patent merges the functions of the substrate, circuit carrier, and protective structure into a single integrated component. The substrate simultaneously provides mechanical support, electrical connectivity, and protection for circuit elements, eliminating the need for separate packaging gel layers and reducing overall structure complexity and manufacturing cost.
3Reliability
If multiple stacked package structures are implemented to achieve system integration, then electrical function is enhanced, but device complexity increases
Solution Approach 1:
The patent resolves device complexity by transitioning from vertical stacking to horizontal integration on a single substrate plane. Circuit patterns, conductive elements, and functional components are arranged laterally across the substrate surface, eliminating the need for multiple stacked packages and simplifying the overall device structure while maintaining enhanced electrical functionality.
Solution Approach 2:
The patent implements multi-functionality within a single substrate structure, where the substrate simultaneously serves as the mechanical base, electrical interconnect, signal routing medium, and protective platform. This universal design consolidates multiple functions that previously required separate stacked components, thereby reducing device complexity while maintaining electrical performance.
Data Source
AI summary
An electronic package is provided, in which a cover layer is embedded in a circuit structure to form a groove, and an electronic element is disposed on the cover layer in the groove. A cladding layer encapsulates the electronic element, and an external connection structure is disposed on the circuit structure and the cladding layer. Therefore, the electronic element is embedded in the groove, such that a thickness of the electronic package can be greatly reduced to meet the requirement of thinning.