Grooved Source Contact Reduces Resistance in MOSFET
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Solution Overview
Problem
Existing power supply semiconductor devices face challenges in reducing contact resistance and increasing integration density while maintaining power efficiency, particularly in low-voltage operations.
Innovation Solution
A discrete power supply semiconductor device is fabricated using a metal-oxide-semiconductor field-effect-transistor (MOSFET) with trench patterns and shield electrodes, where a channel layer is formed using epitaxial growth, and source regions are implanted at inclined sidewalls of grooves to reduce contact resistance and enhance power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar source contact structure is used, then the manufacturing process is simple, but the contact resistance is high and power efficiency is reduced
Solution Approach 1:
The source contact structure transitions from a planar two-dimensional configuration to a three-dimensional grooved structure with inclined sidewalls. This dimensional change increases the contact area between the source electrode and source region, thereby reducing contact resistance and improving power efficiency while maintaining manufacturing feasibility through modified implantation and etching processes
2Reliability
If the contact area between source electrode and source region is increased, then contact resistance is reduced, but the device area increases reducing integration density
Solution Approach 1:
The grooved source contact structure is nested within the existing trench gate structure. The grooves are formed in the source region between the trench patterns, utilizing the vertical and lateral space efficiently. This nesting approach increases the contact area without significantly expanding the overall device footprint, thereby maintaining high integration density while reducing contact resistance
3Reliability
If impurity bodies are formed in the channel layer, then source regions can be positioned at inclined sidewalls, but the fabrication process complexity increases
Solution Approach 1:
Impurity bodies are formed in the channel layer at predetermined locations before the groove formation process. This preliminary action establishes the exact positions where grooves will be etched and where source regions will be implanted, ensuring precise control over the final source contact geometry. This sequencing simplifies the overall process by pre-defining critical dimensions and locations, reducing the complexity of subsequent steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced contact resistance, improved power efficiency, and enhanced switching performance by increasing the contact area between the source electrode and source region, while preventing electrical shorts.
Implementation Method 1
forming a lower channel layer on the substrate using an epitaxial growth process, and forming an upper channel layer on the lower channel layer using an epitaxial growth process
Data Source
AI summary
In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.