Grooved Wiring Structure for Thinner Electronic Packages
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the presence of a die attach film between the semiconductor chip and the wiring structure, which hinders the thinning of the overall package thickness.
Innovation Solution
The proposed electronic package design features a wiring structure with a groove space, where the electronic element is embedded within the encapsulation layer, eliminating the need for a die attach film. This design allows for the thinning of the package thickness by forming the wiring structure with a groove space after removing the carrier board and conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a die attach film is formed between the semiconductor chip and the wiring structure, then the electrical connection is ensured, but the overall thickness of the semiconductor package cannot be thinned
Solution Approach 1:
The invention extracts and removes the die attach film from the package structure. By eliminating this intermediate layer, the patent achieves direct bonding between the semiconductor chip and wiring structure, thereby reducing package thickness while maintaining connection reliability through direct electrical contact.
Solution Approach 2:
The patent embeds the semiconductor chip directly into the wiring structure without an intermediate die attach film. The chip is nested within the package structure and directly bonded to the wiring structure, eliminating the need for a separate adhesive layer and reducing overall thickness.
2Ease of manufacture
If a die attach film is used to bond the semiconductor chip, then the bonding process is simplified, but the package thickness increases and miniaturization is hindered
Solution Approach 1:
The invention merges the semiconductor chip bonding process with the wiring structure formation process. By directly bonding the chip to the wiring structure without a separate die attach film, the patent simplifies the overall manufacturing process while reducing package thickness, eliminating the need for additional adhesive material and processing steps.
3Length of moving object
If the semiconductor chip is directly bonded to the wiring structure without a die attach film, then the package thickness is reduced, but the risk of peeling and void issues increases
Solution Approach 1:
The patent employs a temporary carrier substrate during the bonding process that is removed after bonding. This temporary support structure provides mechanical strength during manufacturing but is discarded afterward, allowing direct chip-to-wiring bonding without permanent adhesive layers that could cause peeling or void issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the thinning of the electronic package, addressing the demand for miniaturization while eliminating the need for a die attach film, which reduces the risk of peeling and void issues.
Implementation Method 1
the encapsulation layer has a first surface and a second surface opposing the first surface, and the second surface of the encapsulation layer is bonded to the wiring structure
Data Source
AI summary
An electronic package and a manufacturing method thereof are provided, in which a groove space for accommodating an electronic element is formed on a wiring structure, and an encapsulation layer is formed on the wiring structure to cover the electronic element. Via the design of the groove space, the overall thickness of the electronic package can be easily thinned to meet the demand for miniaturization.