Transition-Layer Ground Bus for Ultra-Low-Voltage Standby ICs
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Solution Overview
Problem
Modern integrated circuits face challenges in reducing power consumption during low power standby mode due to the need for the transition layer to operate at high power supply voltages, making it difficult to achieve significant voltage-based decreases in power consumption.
Innovation Solution
A dedicated ground bus (GNDx) is implemented within the IC, driven by an on-chip charge pump to create a negative voltage difference between the Vdd power rail and the GNDx, allowing the transition layer to operate at reduced voltage levels, such as from 1.2V to 0.6V, while maintaining deterministic operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transition layer operates at high power supply voltage to remain operational during standby mode, then the transition layer can interface between core logic and I/O sections, but power consumption cannot be significantly reduced
Solution Approach 1:
The patent divides the ground reference into two separate systems: a first ground bus (GND1) for the transition layer and a second ground bus (GND2) for the I/O interface banks. This segmentation allows the transition layer to operate with a higher voltage potential difference (VDD1 to GND1) while the I/O interface banks operate with a lower voltage potential difference (VDD2 to GND2), enabling the transition layer to remain operational during standby mode without requiring the entire IC to maintain high voltage levels.
Solution Approach 2:
The patent applies different voltage characteristics to different sections of the IC. The transition layer section maintains high voltage capability (VDD1-GND1) locally, while the I/O interface banks section operates at low voltage (VDD2-GND2). This local quality differentiation allows each section to operate optimally for its specific function, with the transition layer capable of standby operation while the I/O section consumes minimal power.
2Use of energy by moving object
If the operating supply voltage is reduced to decrease power consumption, then power draw reduces by V2/R factor, but the transition layer cannot remain operational
Solution Approach 1:
The patent segments the power supply system into two independent voltage domains. The first voltage domain (VDD1-GND1) supplies the transition layer with sufficient voltage headroom to remain operational at reduced clock frequencies during standby. The second voltage domain (VDD2-GND2) supplies the I/O interface banks at lower voltage to minimize power consumption. This segmentation resolves the contradiction by allowing voltage reduction overall while preserving transition layer functionality.
Solution Approach 2:
The first ground bus (GND1) acts as an intermediary reference that enables the transition layer to operate with a higher potential difference (VDD1 to GND1) without requiring the entire system to maintain high voltage. This intermediary ground reference allows the transition layer to function as a voltage translator between the high-voltage-capable core logic and the low-voltage I/O interface banks, enabling standby mode operation with reduced power consumption.
3Use of energy by moving object
If clock frequency is reduced in standby mode, then power consumption decreases, but response time to external events increases
Solution Approach 1:
The patent enables dynamic operation of the transition layer during standby mode by providing it with a dedicated voltage domain (VDD1-GND1) that maintains sufficient voltage headroom. This allows the transition layer to operate at reduced clock frequencies (lower power consumption) while still maintaining the capability to respond to external events, as the voltage levels remain adequate for deterministic operation even at lower speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power draw by up to 75% in the core logic section and enables the transition layer to remain operational, achieving lower power consumption during standby mode without compromising deterministic operation.
Implementation Method 1
A dedicated ground bus (GNDx) is implemented within the IC, driven by an on-chip charge pump to create a negative voltage difference between the Vdd power rail and the GNDx
Data Source
AI summary
A core logic portion of a clocked digital circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a low power standby mode (LPSM). The standby mode power voltage is too low relative to normal ground to deterministically drive a transition logic portion of the circuit. However, a special ground bus (GNDx) is provided in the transition logic portion and that special ground bus (GNDx) is pulled down to a negative voltage below normal ground when the circuit is switched into the low power standby mode (LPSM).