Ground-Referenced Chip-to-Chip Encryption at Frame Boundaries

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Solution Overview

Problem

In chip-to-chip communication systems with ground referenced signaling, ensuring simultaneous availability of session keys for secure data transmission across different software protocol stacks and maintaining synchronization during transitions from non-secure to secure states is challenging, particularly in the presence of bit errors.

Innovation Solution

Implementing synchronized encryption and decryption timing by coordinating key synchronization frames to ensure both link partners enter a secure state simultaneously, using TX and RX datalink logic to manage session keys and transition from plaintext to encrypted frames at the same frame and flit level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If key synchronization is performed to ensure simultaneous availability of session keys at both link partners, then security reliability is improved, but the complexity of coordinating encryption timing across different software protocol stacks increases

Engineering Contradiction:
Improvesecurity reliabilityVSAvoidcoordination complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs key synchronization and security state coordination as preliminary actions before actual encrypted data transmission begins. The initiating link partner sends a key synchronization frame that includes a frame count value, and both link partners use this information to pre-coordinate their encryption/decryption timing. This preliminary coordination ensures that when encrypted transmission starts, both ends are simultaneously ready with matching session keys and synchronized encryption states, eliminating the need for complex real-time coordination during data flow.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If continuous frame transmission is maintained to preserve synchronization, then link stability is improved, but the difficulty of managing transition from non-secure to secure state increases

Engineering Contradiction:
Improvelink stabilityVSAvoidtransition management difficulty
Core Design Contradiction:
Stability of the object's compositionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the transition to secure state into distinct phases: (1) key synchronization phase where a key synchronization frame is exchanged and frame count values are coordinated, (2) transition execution phase where both link partners independently switch to encrypted mode at the same frame boundary, and (3) confirmed secure operation phase. This segmentation allows continuous frame transmission to be maintained throughout, while the transition management is simplified by breaking it into discrete, coordinated steps with clear synchronization points at frame boundaries.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If synchronized encryption is implemented at frame and flit level, then encryption precision is improved, but the device complexity for managing TX and RX datalink logic increases

Engineering Contradiction:
Improveencryption precisionVSAvoiddatalink logic complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the initiating link partner sends a key synchronization frame containing a frame count value, and the responding link partner sends back a key synchronization acknowledgement frame. Both TX and RX datalink logic monitor frame counters and use this feedback to independently determine when to switch to encrypted mode. This feedback-based approach enables precise synchronized encryption at frame and flit levels while reducing complexity compared to centralized control, as each end autonomously makes the transition decision based on exchanged synchronization information.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250300827A1Synchronizing an encrypted data stream across chip-to-chip ground referenced signaling interconnect
Publication Date: 2025.09.25 NVIDIA CORP
  • US20250300827A1 patent drawing
  • US20250300827A1 patent drawing
  • US20250300827A1 patent drawing

AI summary

A device includes a memory to store a session key, a transmitter (TX) physical layer to transmit frames to a second device over a link, and TX datalink logic coupled to the TX physical layer and the memory. To coordinate synchronized encryption over the link with the second device, the TX datalink logic is to cause a key synchronization frame to be transmitted to the second device, wherein the key synchronization frame comprises a frame count value. The TX datalink logic, in response to receipt of a key synchronization acknowledgement from the second device acknowledging receipt of the key synchronization frame, is further to start encrypting frame data with the session key after transmitting a number of frames corresponding to the frame count value.