Multi-Stage Ground-Sensing Comparator With Low Offset

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Solution Overview

Problem

Existing comparators, particularly those with PMOS input devices, face challenges in sensing ground-level voltages due to high offset and low gain, which limits their efficiency and response time in switching power regulators.

Innovation Solution

A multi-stage comparator design is implemented, featuring a low gain, low input impedance, fully differential common-gate amplifier as the first stage, coupled with a differential input current-mirror amplifier and a bistable SR latch, enhancing gain and response time while minimizing power consumption and offset.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If PMOS input devices are used in comparators to sense ground level, then the comparator can detect zero-level voltages, but the offset increases and gain decreases

Engineering Contradiction:
Improveground level sensing accuracyVSAvoidoffset and gain performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The comparator is divided into multiple functional stages: a differential input stage for ground level sensing, a gain stage for signal amplification, and an output stage for driving the load. This segmentation allows each stage to be optimized independently, with the differential stage focused on accurate ground detection and the gain stage compensating for offset issues.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A carefully designed intermediate gain stage is introduced between the differential input stage and the output stage. This intermediary stage provides the necessary signal amplification and offset correction, allowing the differential stage to maintain its ground sensing accuracy while the overall system achieves the required gain and low offset performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If PMOS input devices are used in comparators, then ground level sensing is enabled, but response time increases and efficiency decreases

Engineering Contradiction:
Improveground level detection capabilityVSAvoidresponse time and efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent optimizes key parameters including transistor dimensions, bias current levels, and load impedances to achieve fast response times. By carefully selecting and adjusting these parameters, the comparator achieves both accurate ground level sensing and fast response, resolving the contradiction between measurement precision and productivity.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If gain is increased in comparators to improve sensing accuracy, then measurement precision improves, but power consumption increases

Engineering Contradiction:
Improvesensing accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The gain function is segmented across multiple stages rather than concentrated in a single high-gain stage. This allows the total gain to be distributed, with each stage contributing a moderate amount of gain, thereby reducing the power consumption required compared to a single high-gain stage while maintaining the same overall sensing accuracy.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7656199B2Fast, low offset ground sensing comparator
Publication Date: 2010.02.02 VIA TECH INC
  • US7656199B2 patent drawing
  • US7656199B2 patent drawing
  • US7656199B2 patent drawing

AI summary

A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion. The single-ended output of the second stage may serve as the input into a latch, which may be a bistable set-reset (SR) latch configured to increase the gain and response time while protecting against multiple switching, with the single-ended output of the latch configured as the output of the comparator.