Grounded Test Line for Display Panel Layout Optimization
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Solution Overview
Problem
In display panel manufacturing, test switches often cannot be disposed below driving chips due to insufficient space, leading to wasted layout areas, and test lines provide no functional purpose after panel completion, resulting in inefficiencies.
Innovation Solution
Incorporating test lines that are electrically connected to data lines and grounded through pads, providing electrostatic protection and eliminating the need for additional electrostatic protection lines, thus optimizing layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test switches are disposed below driving chips, then test functionality is achieved, but layout space is insufficient and area is wasted
Solution Approach 1:
The test switch is extracted from its traditional location below the driving chip and relocated to the peripheral area of the substrate. This extraction resolves the space conflict by removing the test component from the constrained central area where the driving chip is located, allowing sufficient layout space while maintaining test functionality.
Solution Approach 2:
The test switch is moved from a two-dimensional plane below the driving chip to a different spatial dimension - the peripheral area surrounding the active region. This dimensional relocation allows the test functionality to be achieved without competing for the same limited space under the driving chip, effectively resolving the area constraint.
2Reliability
If test lines are disposed in peripheral areas, then test functionality is achieved, but layout area is wasted as test lines provide no function after panel completion
Solution Approach 1:
The test line is designed to serve dual functions: during manufacturing, it provides test functionality by connecting to the data line and test switch; after panel completion, it continues to provide electrostatic protection for the data line. This multi-functionality eliminates the waste of layout area by ensuring the test line remains useful throughout the product lifecycle.
Solution Approach 2:
The test line, which would normally be discarded as unnecessary after testing, is instead utilized to provide electrostatic protection. This converts what would be a harmful waste of layout area into a beneficial protective function, enhancing device reliability while maintaining layout efficiency.
3Object-affected harmful factors
If additional electrostatic protection lines are added, then electrostatic protection is provided, but layout area increases
Solution Approach 1:
The test line is designed to serve dual functions: during manufacturing, it provides test functionality by connecting to the data line and test switch; after panel completion, it continues to provide electrostatic protection for the data line. This multi-functionality eliminates the waste of layout area by ensuring the test line remains useful throughout the product lifecycle.
Solution Approach 2:
The test line structure serves itself by providing electrostatic protection without requiring separate dedicated protection lines. The same conductive path used for testing during manufacturing automatically becomes the electrostatic protection path after completion, eliminating the need for additional protective structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The grounded test lines effectively protect components from static electricity damage while conserving layout space by serving both testing and protection functions post-manufacturing.
Implementation Method 1
The at least one test line is grounded through the at least one first pad. The grounded at least one test line provides the electrostatic protection function, and thus the components (e.g., the pixel structures etc.) of the display panel are less likely to be damaged by static electricity.
Data Source
AI summary
A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.


