Grounded Through Insulating Vias for Corrosion-Safe Die Stacking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integration of multiple semiconductor devices in wafer-level packaging poses challenges due to issues such as electron accumulation leading to corrosion, particularly in the exposure of through semiconductor vias and through insulating vias during the thinning process.

Innovation Solution

The use of electrically grounded through insulating vias (TIVs) that create a path to deplete accumulated electrons, combined with hybrid bonding processes and encapsulant materials to manage electron accumulation and corrosion, allows for the integration of multiple dies in a single package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through insulating vias are exposed during the thinning process, then electrical connection is established, but electron accumulation causes corrosion

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidelectron accumulation corrosion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful electron accumulation effect into a beneficial grounding function. By intentionally exposing through insulating vias that are electrically connected to ground, the accumulated electrons are drained to ground potential, transforming the corrosion-causing electron accumulation into a useful electron dissipation pathway that protects the device

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The through insulating vias serve as an intermediary element between the exposed semiconductor regions and ground. These vias act as a mediator that provides a controlled electrical pathway to ground, enabling safe dissipation of accumulated electrons while maintaining the insulating function where needed

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple dies are integrated in wafer-level packaging, then manufacturing efficiency is improved, but process complexity increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidpackaging process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the wafer into multiple die regions, each capable of independent processing and packaging. This segmentation allows parallel processing of multiple dies while maintaining standardized procedures for each unit, thereby increasing overall manufacturing efficiency without proportionally increasing the complexity of individual die handling

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs universal through insulating via structures that serve multiple functions: providing electrical grounding, enabling electron dissipation, and serving as alignment references. This multi-functionality reduces the number of separate components and processes needed, thereby managing complexity while achieving multiple objectives

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively resolves the issue of electron accumulation-induced corrosion, enabling the successful integration and packaging of multiple semiconductor devices with improved reliability and reduced manufacturing costs.

Implementation Method 1

The first TIVs are electrically grounded through the contact vias... create a path to deplete accumulated electrons

Methodology Applied
Scientific EffectElectron conduction: Conduction (electrical)

Data Source

PatentUS12166014B2Manufacturing method of package
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12166014B2 patent drawing
  • US12166014B2 patent drawing
  • US12166014B2 patent drawing

AI summary

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.