Grounded Adhesive Transfer Stamp for ESD-Safe Chip Placement

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Solution Overview

Problem

Conventional methods for transferring semiconductor chips are prone to damage from electrostatic discharges, and existing technologies lack effective solutions for preventing electrostatic discharge (ESD) during the transfer process, particularly for sensitive optoelectronic chips.

Innovation Solution

An adhesive transfer stamp comprising an electrically insulating volume region with an integrated electrically conductive element connected to a ground conductor, which dissipates electrostatic charges, combined with a transparent carrier for optical alignment, effectively suppresses ESD pulses and prevents damage to the semiconductor chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transfer methods are used, then the transfer process is simple, but electrostatic discharge damage occurs to semiconductor chips

Engineering Contradiction:
Improveprotection against electrostatic dischargeVSAvoidstructure of transfer stamp
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transfer stamp combines electrically insulating material (for ESD protection) with electrically conductive elements (for charge dissipation) to create a composite structure that provides both protection and functionality, resolving the contradiction between reliability improvement and structural complexity

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The electrically conductive elements act as intermediaries between the insulating volume region and the ground conductor, providing a controlled path for charge dissipation while maintaining the overall insulating structure needed for ESD protection

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the volume region is made transparent, then optical alignment is enabled, but manufacturing complexity increases

Engineering Contradiction:
Improveoptical alignment precisionVSAvoidmanufacturing of transparent insulating volume region
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent specifies a transparency parameter (extinction coefficient k < 10^-3 at 550 nm) for the insulating material, transforming a qualitative requirement into a quantifiable manufacturing specification that enables precise optical alignment while providing clear manufacturing criteria

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents electrostatic discharge damage to semiconductor chips during transfer by dissipating charges to a ground conductor, allowing for precise optical alignment and successful placement without damaging the chips, especially for sensitive optoelectronic components.

Implementation Method 1

an electrically conductive element, which is provided for being electrically conductively connected to a ground conductor during operation and is configured to dissipate electrical charges from the semiconductor chip to the ground conductor

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

electrically conductive element, which is provided for being electrically conductively connected to a ground conductor

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

optical alignment with the aid of a camera system through the transparent adhesive transfer stamp is advantageously possible

Methodology Applied
Scientific EffectLight transmission: Light

Data Source

PatentUS12106980B2Adhesive transfer stamp and method for transferring a semiconductor chip using an adhesive transfer stamp
Publication Date: 2024.10.01 OSRAM OPTO SEMICON GMBH & CO OHG
  • US12106980B2 patent drawing
  • US12106980B2 patent drawing
  • US12106980B2 patent drawing

AI summary

In an embodiment an adhesive transfer stamp for transferring semiconductor chips includes a volume region including an electrically insulating material, at least one adhesive surface configured to receive a semiconductor chip and an electrically conductive element configured to electrically conductively connected to a ground conductor during operation and to dissipate electrical charges from the semiconductor chip to the ground conductor, wherein the volume region is embodied as a solid body, and wherein the volume region has at least one stepped structure.