Group-Based Buffering for Parallel Data Readout in Shared Interconnects
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Solution Overview
Problem
In integrated circuits, shared interconnects lead to head of line blocking when multiple hardware modules try to send data to the same destination simultaneously, causing requests to be queued and delaying transmission.
Innovation Solution
Assigning destination circuits into groups, with each source circuit having a request buffer and group buffers corresponding to these groups, allowing parallel transmission of requests across different groups through a shared interconnect, thereby minimizing head of line blocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a shared interconnect is used to connect hardware modules to destinations, then space requirements are reduced, but head of line blocking occurs when multiple modules compete for the same destination
Solution Approach 1:
The patent segments the destination address space into multiple groups (e.g., group 0, group 1, etc.). Each source circuit maintains separate buffers for each group, allowing independent management of requests destined for different groups. This segmentation enables parallel processing of requests to different groups, preventing head of line blocking while using a shared interconnect, thus resolving the contradiction between space efficiency and transmission productivity.
2Productivity
If independent interconnects are provided for every hardware module to every destination, then data transmission efficiency is maximized, but space requirements become prohibitive
Solution Approach 1:
The shared interconnect is designed to be universal, serving multiple source circuits and multiple destination groups simultaneously. By implementing group-based buffering and parallel request submission, the single shared interconnect achieves multi-functionality that approximates the performance of multiple dedicated interconnects while consuming significantly less space, thus resolving the contradiction between productivity and space requirements.
3Device complexity
If requests are queued in a single buffer, then device complexity is reduced, but transmission delays increase due to head of line blocking
Solution Approach 1:
The single buffer is segmented into multiple group-specific buffers (e.g., buffer 205 for group 0, buffer 210 for group 1). Each buffer independently manages requests for its assigned group, allowing requests for different groups to be processed in parallel without blocking each other. This segmentation reduces transmission delays while maintaining manageable complexity through systematic organization, resolving the contradiction between device complexity and time loss.
Data Source
AI summary
Embodiments herein describe assigning requests from hardware modules that are transmitted by a shared interconnect to destinations (e.g., workers) in the same integrated circuit (IC) into groups. For example, the destinations can be assigned into respective groups. When a request is received, a group classifier can use the destination address in the request to identify its group. The request can be stored in a request buffer, while the location of the request in the request buffer is stored in a group buffer. Each hardware module can include a request buffer and a group buffer for each group in the system.