Group Control Circuit for Semiconductor Memory Voltage Stability

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Solution Overview

Problem

Integrated circuits with semiconductor memory apparatuses face malfunctions due to sudden drops in supply voltage caused by simultaneous activation of internal circuits, which is exacerbated by decreasing voltage levels.

Innovation Solution

A group control circuit with a parallel structure that generates sequential activation selection signals using synchronized first and second edge clock signals with different phases, allowing for staggered activation of internal circuits to manage current demand and prevent voltage drops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple internal circuits are activated simultaneously to improve processing speed and functionality, then the circuit functionality is enhanced, but the supply voltage suddenly drops causing malfunctions

Engineering Contradiction:
Improveprocessing speedVSAvoidcircuit stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the simultaneous activation of multiple internal circuits into sequential activation stages. The group control circuit separates circuits into different groups and activates them at different time points using edge clock signals, preventing simultaneous current draw that causes voltage drops while maintaining overall circuit functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses edge clock signals to preliminarily determine the activation timing of different circuit groups before actual operation. By synchronizing circuit activation with specific clock edges, the system prepares and coordinates current draw in advance, preventing sudden voltage drops while enabling systematic circuit activation.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If the supply voltage level is reduced to improve power efficiency, then energy consumption is decreased, but the circuit becomes more susceptible to voltage drops and malfunctions

Engineering Contradiction:
Improvepower efficiencyVSAvoidvoltage stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent employs periodic clock signals with different edges to control the sequential activation of circuit groups. This periodic control mechanism ensures that current draw is distributed over time rather than occurring simultaneously, maintaining stable voltage levels even when operating at reduced supply voltages for power efficiency.

Inventive Principle:
Principle #19Periodic action

3Reliability

If a sequential control mechanism is implemented to prevent voltage drops, then voltage stability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a group control circuit as an intermediary between the clock signal source and the internal circuits. This intermediary uses edge clock signals to coordinate and control the sequential activation of different circuit groups, providing a systematic and manageable approach to voltage stability without requiring complex point-by-point control of each circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11315615B1Group control circuit and semiconductor memory apparatus including the same
Publication Date: 2022.04.26 SK HYNIX INC
  • US11315615B1 patent drawing
  • US11315615B1 patent drawing
  • US11315615B1 patent drawing

AI summary

A group control circuit includes a selection signal generation circuit and first and second activation selection circuits. The selection signal generation circuit generates a source selection signal by synchronizing an entry control signal. The first activation selection circuit generates a plurality of first activation selection signals in synchronization with a first edge clock signal. The second activation selection circuit generates a plurality of second activation selection signals in synchronization with a second edge clock signal. The first and second activation selection circuits have a parallel structure.