Group III Nitride on Silicon Integration via Multi-Layer Buffer
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Solution Overview
Problem
The integration of Group III nitride materials with silicon substrates is challenging due to lattice mismatch and differing crystal structures, limiting the availability and cost-effectiveness of suitable substrates for semiconductor devices like LEDs.
Innovation Solution
A method involving the formation of a structure with a (100) silicon layer, a (111) silicon layer, a Group III nitride material layer, and a dielectric material layer, where openings are created to expose the silicon surface, followed by the growth of an epitaxial semiconductor material layer, using techniques such as oxidation and conformal dielectric material liners to facilitate direct contact and reduce lattice mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Group III nitride materials are grown on conventional substrates like sapphire, then device performance is maintained, but substrate cost and availability are worsened
Solution Approach 1:
The patent introduces a multi-layer intermediary structure consisting of a (100) silicon layer, a (111) silicon layer, and a buffer layer as a mediator between the silicon substrate and the Group III nitride material. This intermediary structure gradually transitions the lattice mismatch, allowing growth on inexpensive silicon substrates while maintaining device performance that would otherwise require expensive sapphire substrates.
2Ease of manufacture
If Group III nitride materials are integrated directly on silicon substrates, then substrate cost is reduced, but lattice mismatch and crystal structure differences worsen integration difficulty
Solution Approach 1:
The patent segments the interface between silicon and Group III nitride into multiple distinct layers: a (100) silicon layer, a (111) silicon layer, and a buffer layer. Each layer serves a specific function in managing the lattice mismatch and crystal structure transition, making the overall integration process manageable despite the inherent difficulties of direct silicon-nitride integration.
3Reliability
If lattice matched freestanding GaN and AlN substrates are used, then device performance is improved, but availability and cost are worsened
Solution Approach 1:
The patent creates an artificial copy of the lattice-matched interface structure by fabricating a multi-layer silicon and buffer layer system that replicates the beneficial properties of freestanding lattice-matched substrates. This copied structure allows device performance comparable to expensive freestanding substrates while using abundant, inexpensive silicon wafers as the base material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the effective integration of Group III nitride materials with silicon substrates, improving the feasibility and cost-effectiveness of semiconductor device production by reducing lattice mismatch and enhancing epitaxial growth, thus addressing the limitations of conventional substrates.
Implementation Method 1
a (111) silicon layer located on an uppermost surface of the (100) silicon layer
Implementation Method 2
An oxidation process is performed to form an oxide plug within the exposed portion of the (111) silicon layer
Implementation Method 3
An epitaxial semiconductor material layer is formed on a remaining portion of the exposed surface of the (100) silicon layer
Data Source
AI summary
Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.