Group III Nitride Substrate Fabrication via Metal-Buried Stripe Segmentation
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Solution Overview
Problem
Current methods for producing large-area nonpolar/semipolar GaN substrates often result in high stacking fault densities, which degrade the efficiency of optoelectronic devices due to basal plane stacking faults, and existing solutions either limit wafer size or introduce polycrystalline growth at gaps between tiled strips.
Innovation Solution
A method involving growing a group III nitride bulk crystal along the c-direction, covering the polar c-plane with metal, slicing into strips, and aligning them to grow in supercritical ammonia, where the nitride crystal fuses strips together, minimizing polycrystal formation and concentrating stacking faults in bundles separated by large, fault-free regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If large-area nonpolar/semipolar GaN substrates are produced by current methods, then substrate area is increased, but stacking fault density increases degrading device efficiency
Solution Approach 1:
The substrate is divided into multiple regions with different stacking fault densities. By segmenting the growth process and using different seed crystal orientations in different regions, the patent creates a mosaic pattern where some regions have low stacking fault density (suitable for devices) while others have high density (acting as defect sinks). This segmentation allows large substrate area while preserving manufacturing precision in critical device regions.
Solution Approach 2:
Different regions of the substrate are given different crystallographic orientations and stacking fault characteristics. The patent uses local quality by making specific areas (device regions) have superior crystal quality with low stacking fault density, while other areas (non-device regions) tolerate higher defect densities. This is achieved by selective seed crystal placement and orientation control during the growth process.
2Manufacturing precision
If wafer size is limited to avoid stacking faults, then stacking fault density is reduced, but substrate area is decreased
Solution Approach 1:
Rather than uniformly limiting wafer size, the patent segments the wafer into multiple functional zones. Device fabrication regions are kept relatively small to maintain low stacking fault density, while the overall substrate area is expanded by adding non-device regions that accommodate higher defect densities. This allows the substrate area to increase without compromising the manufacturing precision in critical device areas.
3Area of stationary object
If strips are tiled to increase substrate area, then area is increased, but polycrystalline growth occurs at gaps between strips
Solution Approach 1:
The patent merges multiple crystal growth processes into a single continuous growth operation. Instead of separately growing and tiling strips (which creates gaps and polycrystalline regions), the invention uses a unified growth process where multiple seed crystals are simultaneously grown together in a single reactor chamber. This merging of growth processes eliminates gaps between strips and prevents polycrystalline formation at boundaries, while still achieving large substrate area through the mosaic arrangement of differently oriented regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a large, fault-free area for device fabrication with over 80% of stacking faults clustered outside usable regions, enhancing the efficiency of optoelectronic devices by minimizing polycrystalline growth and maintaining high crystal quality.
Implementation Method 1
growing group III nitride crystal in supercritical ammonia... the nitride crystal fuses strips together
Data Source
AI summary
Group III nitride substrate having a first side of nonpolar or semipolar plane and a second side has more than one stripe of metal buried, wherein the stripes are perpendicular to group III nitride's c-axis. More than 90% of stacking faults exist over metal stripes. Second side may expose a nonpolar or semipolar plane. Also disclosed is a group III nitride substrate having a first side of nonpolar or semipolar plane and a second side with exposed nonpolar or semipolar plane. The substrate contains bundles of stacking faults with spacing larger than 1 mm. The invention also provides methods of fabricating the group III nitride substrates above.