Self-Aligned Gate Masking for Group III-Nitride Transistor Source/Drain Placement
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Solution Overview
Problem
Conventional lithographic techniques struggle to reliably place source/drain implants close to the gate metal in high-frequency transistor devices, such as those operating above the X-band frequency range, due to limitations in precision and reliability.
Innovation Solution
The method involves forming a masking gate with a specific structure and using it as an implant mask to self-align the source/drain regions within 100 to 300 nm of the gate metal, allowing for precise placement and reliable formation of source/drain implants using a protective layer and resist layers with different developer sensitivities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic techniques are used to place source/drain implants, then the manufacturing process is simple, but the manufacturing precision and reliability deteriorate due to inability to reliably place implants close to gate metal
Solution Approach 1:
The gate electrode is formed first as a preliminary structure that serves as a self-aligned mask for subsequent source/drain implantation. This preliminary positioning action eliminates the need for separate lithographic alignment steps, achieving sub-100nm precision placement of implants relative to the gate metal while managing process complexity through self-alignment
Solution Approach 2:
A protective layer is introduced as an intermediary between the gate electrode and the source/drain implantation process. This intermediary layer allows precise control of implant placement distance (100-300nm) from the gate metal while protecting the gate structure during fabrication, resolving the contradiction between precision placement and process complexity
2Productivity
If source/drain implants are placed closer to gate metal, then parasitic capacitance is reduced and device efficiency improves, but manufacturing precision requirements increase beyond conventional lithographic capabilities
Solution Approach 1:
The gate electrode structure itself serves as the alignment reference for source/drain implantation through the self-aligned masking process. The gate electrode 'services its own function' as a positioning mask, enabling precise placement (100-300nm from gate edge) without requiring external lithographic alignment, thus achieving high device efficiency while maintaining manufacturability
Solution Approach 2:
The protective layer introduces a vertical dimension to the fabrication process, allowing precise lateral placement control through vertical layer thickness control. By controlling the protective layer thickness and using it as an etch stop, the method achieves precise 100-300nm placement of source/drain regions relative to the gate electrode without relying on lateral lithographic precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of source/drain implants very close to the gate metal with high precision, improving the performance of high-frequency transistors by reducing parasitic capacitance and enhancing device efficiency.
Implementation Method 1
implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask
Data Source
AI summary
Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.