Group III-V Semiconductor Device With Current Blocking Layer

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Solution Overview

Problem

The integration of Group III-V semiconductors with silicon-based devices is limited due to lattice constant and thermal expansion coefficient differences, leading to defects and challenges in controlling electrical characteristics.

Innovation Solution

A semiconductor device structure is implemented with a current blocking layer between the substrate and active layer, using a selective area growth process, which includes a buffer and barrier layer to reduce defects and improve crystallinity, and employs Group III-V materials like InGaAs, InP, and InAs for the active layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Group III-V material is applied onto a silicon substrate, then the device can achieve higher performance and integration density, but defects are formed at the interface due to lattice constant and thermal expansion coefficient differences

Engineering Contradiction:
Improvedevice performanceVSAvoidinterface defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A current blocking layer is introduced as an intermediary between the silicon substrate and the Group III-V active layer. This intermediate layer serves as a mediator that addresses the interface compatibility issues by providing a transition zone that reduces defect formation while enabling the Group III-V material to function effectively on the silicon substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device structure is segmented into distinct functional layers: a silicon substrate, a current blocking layer, and a Group III-V active layer. This segmentation allows each layer to be optimized independently, with the current blocking layer specifically designed to handle the interface compatibility issues between silicon and Group III-V materials.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a Group III-V material is applied onto a silicon substrate, then the device can achieve higher performance, but electrical characteristics become difficult to control

Engineering Contradiction:
Improvedevice performanceVSAvoidelectrical characteristic control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The current blocking layer acts as an intermediary that provides control over electrical characteristics. By positioning this layer between the silicon substrate and the Group III-V active layer, the patent enables independent optimization of electrical properties, making it easier to control leakage current and overall device performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If a current blocking layer is interposed between substrate and active layer, then leakage current is suppressed and electrical characteristics are improved, but device structure becomes more complex

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidmulti-layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The harmful leakage current is extracted or blocked by introducing a dedicated current blocking layer. This layer specifically addresses the electrical control issue by preventing unwanted current paths, thereby improving overall device performance despite the added structural complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses leakage current and enhances electrical characteristics, achieving improved performance and reliability by trapping defects and improving crystallinity of the active layer.

Implementation Method 1

a current blocking layer between the substrate and the active layer

Methodology Applied
Scientific EffectCharge blocking: Electrical Resistance

Implementation Method 2

a multi-layer structure disposed on a portion of the substrate... formed via a selective area growth (SAG) process

Methodology Applied
Scientific EffectSelective area growth: Epitaxy

Data Source

PatentUS9312377B2Semiconductor devices and methods of manufacturing the same
Publication Date: 2016.04.12 SAMSUNG ELECTRONICS CO LTD
  • US9312377B2 patent drawing
  • US9312377B2 patent drawing
  • US9312377B2 patent drawing

AI summary

Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.