Group III-V Device Structure With Through Via

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Solution Overview

Problem

Existing Group III-V device structures, used in semiconductor technology, face challenges such as high electron mobility and high-frequency signal transmission but are not entirely satisfactory, particularly in preventing current flow without a gate voltage due to their normally ON state, which is a concern in power applications.

Innovation Solution

A Group III-V device structure is developed with a through via structure, including a semiconductor substrate with a nucleation layer, transition layer, buffer layer, and channel layer, where a hetero-junction forms a two-dimensional electron gas (2DEG) that is depleted by a gate electrode to convert the device from a normally ON to a normally OFF state, and a through via structure is formed to connect the substrate to a package substrate, reducing inductance and contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Group III-V device structure is used to achieve high electron mobility and high-frequency signal transmission, then the device performance is improved, but the device remains in a normally ON state which causes unwanted current flow in power applications

Engineering Contradiction:
Improvedevice performanceVSAvoidunwanted current flow
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by introducing a gate electrode structure that pre-establishes the capability to deplete the two-dimensional electron gas at the hetero-junction. The gate electrode is positioned and configured in advance to exert control over the channel, enabling the device to be turned OFF when needed. This preliminary setup of the control mechanism allows the device to transition from a normally ON state to a controllable state, preventing unwanted current flow before it becomes a problem in power applications.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If a through via structure is formed to connect substrate to package substrate, then inductance and contact resistance are reduced, but the fabrication process becomes more complex

Engineering Contradiction:
Improveinductance and contact resistanceVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the through via formation into distinct stages: first forming the via hole through the substrate, then filling it with conductive material to create the through via structure. This segmented approach allows for better control over each step of the process, enabling the reduction of inductance and contact resistance while managing the fabrication complexity through systematic process breakdown.

Inventive Principle:
Principle #1Segmentation

3Temperature

If the semiconductor substrate is thinned to improve heat dissipation, then thermal performance is improved, but the substrate becomes more susceptible to mechanical stress and defects

Engineering Contradiction:
Improveheat dissipationVSAvoidmechanical strength
Core Design Contradiction:
TemperatureVSStrength

Solution Approach 1:

The patent applies local quality by selectively thinning the semiconductor substrate in specific regions while maintaining appropriate thickness in other areas. This localized thinning approach allows for improved heat dissipation in critical areas where thermal management is most needed, while preserving the mechanical strength and structural integrity of the substrate in regions that require support. The selective modification of substrate thickness creates different local properties optimized for different functional requirements.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances the reliability and performance of Group III-V devices by preventing unwanted current flow and improving heat dissipation, reducing inductance and contact resistance, and simplifying the fabrication process by eliminating the need for a carrier substrate, thus addressing the limitations of existing Group III-V device structures.

Implementation Method 1

a hetero-junction forms a two-dimensional electron gas (2DEG) that is depleted by a gate electrode to convert the device from a normally ON to a normally OFF state

Methodology Applied
Scientific EffectTwo-dimensional electron gas (2DEG) formation:

Implementation Method 2

a hetero-junction forms a two-dimensional electron gas (2DEG) that is depleted by a gate electrode

Methodology Applied
Scientific EffectElectron depletion:

Data Source

PatentUS10163707B2Method for forming group III-V device structure
Publication Date: 2018.12.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10163707B2 patent drawing
  • US10163707B2 patent drawing
  • US10163707B2 patent drawing

AI summary

Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.