Convolutional Rate Matching Using Group-Ordered Parity Interleaving
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Solution Overview
Problem
Conventional rate matching circuits for convolutional codes in mobile communication systems have high complexity and require different interleavers for different parity bit streams, limiting their efficiency and performance.
Innovation Solution
A method and apparatus for rate matching that uses identical interleavers for different parity bit streams, performing group multiplexing and puncturing or repeating parity bits to match the data channel rate, reducing complexity and improving channel encoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional rate matching circuits are used with different interleavers for different parity bit streams, then the performance is maintained, but the device complexity increases
Solution Approach 1:
The patent applies universality by using a single interleaver structure that can handle multiple parity bit streams (P1, P2, P3) from the convolutional encoder. Instead of implementing separate interleavers for each parity stream, one interleaver is configured to interleave all parity bits in a systematic manner, reducing device complexity while maintaining the error correction performance through proper interleaving of all parity information.
2Device complexity
If identical interleavers are used for different parity bit streams, then the device complexity is reduced, but the performance may deteriorate
Solution Approach 1:
The patent applies segmentation by organizing the interleaving process into distinct phases: first interleaving each parity bit stream separately within the single interleaver structure, then performing group multiplexing to combine the interleaved parity bits. This segmented approach within a unified interleaver maintains the performance benefits of separate interleaving while achieving the complexity reduction of identical interleavers.
Solution Approach 2:
The patent resolves the performance concern by introducing a new dimension of organization through group multiplexing. After interleaving parity bits from different streams using the same interleaver, the bits are arranged in group order (all P1 bits, then all P2 bits, then all P3 bits). This dimensional reorganization preserves the diversity benefits of multiple parity streams while enabling the use of identical interleavers.
3Productivity
If rate matching is performed by bit-multiplexing interleaved bits from all parity bit streams, then the data transmission rate is matched, but the device complexity increases
Solution Approach 1:
The patent applies merging by combining the interleaving and rate matching functions into a unified process. The single interleaver performs both interleaving and initial rate matching by selectively outputting interleaved bits in group order. This merging eliminates the need for separate bit-multiplexing circuits that would otherwise be required to combine multiple interleaved streams, reducing device complexity while maintaining flexible rate matching capability.
Data Source
AI summary
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.