Grouped Bit-Line Memory Layout for Higher Density and Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in increasing memory capacity per unit area while maintaining data accuracy and reducing errors, due to increased parasitic capacitance and resistance as the number of memory cells increases, leading to issues with data retention and read accuracy.
Innovation Solution
The memory device design involves dividing bit lines and word lines into groups, with each group connected to specific bit line and word line driver circuits, and overlapping driver circuits with cell arrays in a three-dimensional layout to reduce parasitic capacitance and resistance, using transistors with low off-state current for memory cells and high mobility transistors for driver circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to achieve large storage capacity, then memory capacity per unit area is improved, but parasitic capacitance and resistance of bit lines and word lines are increased, leading to reduced data accuracy and increased error incidence
Solution Approach 1:
The bit lines and word lines are divided into multiple groups, with each group connected to specific driver circuits. This segmentation reduces the number of memory cells connected to each bit line and word line, thereby reducing parasitic capacitance and resistance while maintaining high memory capacity through increased integration density.
Solution Approach 2:
Driver circuits are overlapped with cell arrays in a three-dimensional layout configuration. This vertical stacking approach reduces the planar area occupied by driver circuits, allowing for higher integration density and reduced parasitic effects without compromising data accuracy.
2Quantity of substance
If the area of capacitor is reduced to decrease memory cell area, then memory capacity per unit area is improved, but difference between amounts of electric charge corresponding to different digital values becomes smaller, making it difficult to maintain data accuracy
Solution Approach 1:
By dividing bit lines into multiple groups with dedicated driver circuits, the parasitic capacitance per bit line is reduced. This allows for smaller capacitor areas while maintaining sufficient charge difference for accurate data reading, as each bit line carries less total parasitic load.
3Productivity
If the number of memory cells connected to one bit line is increased to achieve higher integration, then memory capacity per unit area is improved, but parasitic capacitance and resistance of bit line are increased, making it difficult to read data accurately
Solution Approach 1:
Bit lines are divided into multiple groups, each served by dedicated driver circuits. This reduces the number of memory cells per bit line group, lowering parasitic capacitance and resistance while maintaining high overall integration density through the segmented architecture.
Solution Approach 2:
The three-dimensional overlapping layout of driver circuits with cell arrays reduces the planar footprint, allowing for higher integration density without increasing bit line lengths or parasitic effects that would compromise read accuracy.
Data Source
AI summary
An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.