Grouped LDPC Error Correction for Lower-Memory Data Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data processing devices for memory systems face challenges in reducing memory capacity and power consumption while effectively correcting error bits.
Innovation Solution
The proposed data processing device incorporates variable nodes and check nodes that perform error correction through iterative operations, using group state values and flipping functions to determine and correct error bits, thereby reducing memory requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then error correction capability is maintained, but memory capacity and power consumption increase
Solution Approach 1:
The patent divides variable nodes into multiple groups and maintains separate state values for each group rather than a single global state value. This segmentation allows the system to track error patterns in different regions independently, improving error correction capability while using less memory than a fully distributed state approach.
Solution Approach 2:
The patent changes the parameter of state representation from individual node states to group-level state values. By maintaining state values at the group level rather than individual node level, the system reduces memory capacity requirements while still capturing sufficient information for effective error correction through iterative processing.
Solution Approach 3:
The patent applies partial action by updating state values selectively based on detection results from check nodes. Rather than continuously updating all state values, the system performs updates only when errors are detected in specific groups, reducing power consumption while maintaining error correction effectiveness.
2Reliability
If traditional error correction methods are used, then error correction capability is maintained, but power consumption increases
Solution Approach 1:
The patent implements partial action by performing state value updates only when errors are detected in specific variable node groups. The iterative process selectively activates correction operations based on detection results, avoiding unnecessary computations and reducing power consumption compared to continuous full-system correction.
Solution Approach 2:
The patent employs periodic iterative processing where detection and correction operations are performed in cycles. Each iteration checks for errors and updates state values periodically rather than continuously, reducing power consumption while maintaining error correction capability through repeated refinement.
3Measurement precision
If group state values are updated in every iteration, then error correction accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by updating group state values selectively based on detection results rather than in every iteration. When check nodes detect no errors in a group, the state value remains unchanged, avoiding unnecessary write operations and reducing power consumption while maintaining accuracy through targeted updates.
Solution Approach 2:
The patent implements feedback control where detection results from check nodes determine whether state value updates are performed. The system uses feedback from error detection to intelligently control update operations, improving accuracy when needed while conserving power when errors are absent.
Data Source
AI summary
A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.