Grouped Memory Cell Array Architecture for Sense Amplifier Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data sense circuitry and architectures for semiconductor DRAM arrays require a large number of sense amplifiers, leading to increased silicon area and power consumption, especially when implementing dense memory arrays with large word lines.
Innovation Solution
The proposed solution involves a memory cell array architecture with shared word line segments and bit line selection circuitry, allowing for reduced number of data sense/write circuitry by interconnecting multiple memory cells to a single data sense/write circuit, thereby minimizing the number of sense amplifiers required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data sense circuitry is used for each bit line in dense memory arrays, then data sensing capability is maintained, but silicon area and power consumption increase significantly
Solution Approach 1:
Multiple bit lines are merged to share a common data sense/write circuit. The patent groups memory cells and their associated bit lines, allowing a single sense amplifier to service multiple bit lines through selective activation and sharing mechanisms, thereby reducing the total number of sense amplifiers required in dense memory arrays.
Solution Approach 2:
The data sense/write circuit is designed to perform multiple functions by serving multiple bit lines. The circuit can be selectively activated to sense or write data on different bit lines, making it a universal resource that replaces the need for dedicated sense amplifiers for each bit line, thus reducing silicon area while maintaining sensing capability.
2Reliability
If conventional data sense circuitry is used for each bit line in dense memory arrays, then data sensing capability is maintained, but power consumption increases
Solution Approach 1:
Multiple bit lines are merged to share a common data sense/write circuit. The patent groups memory cells and their associated bit lines, allowing a single sense amplifier to service multiple bit lines through selective activation and sharing mechanisms, thereby reducing the total number of sense amplifiers required in dense memory arrays.
Solution Approach 2:
The data sense/write circuit is designed to perform multiple functions by serving multiple bit lines. The circuit can be selectively activated to sense or write data on different bit lines, making it a universal resource that replaces the need for dedicated sense amplifiers for each bit line, thus reducing silicon area while maintaining sensing capability.
3Area of stationary object
If the number of sense amplifiers is reduced through sharing, then silicon area and power consumption decrease, but device complexity increases
Solution Approach 1:
The memory array is segmented into groups of memory cells, with each group associated with a specific data sense/write circuit. Word lines are also segmented into groups, with each group controllable by a single word line. This segmentation allows for systematic sharing of sense amplifiers while maintaining organized control structures that manage the complexity of the shared architecture.
Solution Approach 2:
The patent introduces dynamic control mechanisms including bit line selection circuitry that can selectively activate specific bit lines connected to a shared sense amplifier, and word line grouping that dynamically controls which groups of memory cells are accessed. This dynamic control allows the system to manage complexity by activating only the necessary portions of the shared circuitry at any given time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a more compact and power-efficient memory array design with reduced overhead, enabling denser memory arrays while maintaining effective data sensing and writing capabilities.
Implementation Method 1
charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18
Implementation Method 2
accumulating majority carriers (in this example, 'holes') 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22
Implementation Method 3
a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric
Implementation Method 4
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32
Data Source
AI summary
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled to an associated word line (e.g., a first segment is associated with the first word line and a second segment is associated with the second word line). The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, wherein the body region is electrically floating, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first word line via the first word line segment and a second group of memory cells is coupled to the second word line via the second word line segment wherein at least one memory cell of the first group of memory cells is adjacent to at least one memory cell of the second group of memory cells.