Grouped Memory Cell Read Logic for High-Density Reliability
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Solution Overview
Problem
Conventional memory cells face reliability issues when trying to store multiple bits of data due to physical limitations, leading to difficulties in differentiating charge levels and increased data corruption, especially in higher bit density scenarios like penta-level cells with 32 charge levels.
Innovation Solution
The solution involves performing data operations on grouped memory cells, allowing for the virtual grouping of two or more cells to create a 'supercell' that can store an integer number of bits greater than each individual cell, using a mapping matrix to assign charge levels to bit representations and applying logical operations for read operations, thereby increasing data storage capacity without sacrificing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are designed to store multiple bits of data (higher bit density), then data storage capacity is improved, but reliability deteriorates due to physical limitations and difficulty in differentiating charge levels
Solution Approach 1:
The patent divides a single high-capacity memory cell into multiple lower-capacity sub-cells (e.g., splitting a penta-level cell into multiple binary cells). Each sub-cell stores fewer bits with more stable charge levels, improving reliability. The combined output of these sub-cells achieves the desired total storage capacity while maintaining better differentiation between charge levels in each individual sub-cell.
Solution Approach 2:
The patent transitions from storing multiple bits in a single cell (vertical dimension of capacity) to using multiple cells working together (horizontal dimension of organization). By arranging memory cells in arrays and using bitwise operations across multiple cells, the system achieves high storage capacity while each individual cell maintains reliable, easily-differentiated charge levels.
2Quantity of substance
If more charge levels are used in memory cells to increase bit density, then data storage capacity is improved, but measurement precision deteriorates due to difficulty in differentiating charge levels
Solution Approach 1:
The patent segments high-density storage into multiple low-density sub-cells, each handling fewer charge levels that are easier to differentiate. For example, instead of one cell with 32 charge levels (5 bits), the system uses multiple cells with 2 charge levels each (1 bit), where charge level differentiation is much more precise and reliable.
Solution Approach 2:
The patent replaces direct physical measurement of high-precision charge levels with logical operations on multiple binary cells. Instead of precisely measuring and differentiating between 32 charge levels in one cell, the system uses bitwise AND, OR, and XOR operations across multiple binary cells to achieve the same 5-bit storage with much simpler and more reliable charge level differentiation.
3Quantity of substance
If physical memory cells are added to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple simple memory cells into a unified high-capacity storage unit through logical operations. By combining the outputs of multiple binary cells using bitwise operations (AND, OR, XOR), the system achieves the storage capacity of a single high-density cell while using only simple, well-understood binary memory cell building blocks, thereby reducing overall device complexity.
Solution Approach 2:
The patent creates a universal memory architecture where the same simple binary memory cell design can be used for all storage needs. By using identical binary cells in arrays and applying logical operations, the system achieves multiple functions (high capacity, high reliability, scalability) without requiring different types of specialized memory cells, simplifying manufacturing and device design.
Data Source
AI summary
A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.