Grouped Interconnect Pad Arrays for Simpler 3D Die Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently designing interconnect structures for stacked semiconductor devices, such as 3D integrated circuits, due to complex routing designs that lead to inefficient utilization of conductive lines and increased complexity in electrical connections between semiconductor wafers or dies.
Innovation Solution
The proposed interconnect structure features a simple and efficient routing design with two sets of pads arranged in arrays, where pads are grouped and electrically connected through conductive lines in specific layers, optimizing the use of routing resources and simplifying the design by grouping pads and connecting them via conductive pillars and vias across multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex routing designs are used for interconnect structures, then electrical connections between semiconductor wafers or dies can be established, but the utilization efficiency of conductive lines decreases and design complexity increases
Solution Approach 1:
The routing design is segmented into two distinct sets: first routing resources connecting first pads, and second routing resources connecting second pads. This segmentation simplifies the overall routing complexity by dividing the interconnect design into manageable, independent segments rather than attempting complex all-to-all connections.
Solution Approach 2:
Pads are grouped into sets (first pads and second pads) that share common routing resources. By merging multiple pads into groups that can be collectively connected through shared routing resources, the design reduces the total number of conductive lines needed while maintaining all necessary electrical connections.
2Reliability
If traditional routing designs are used, then all pads can be connected, but the number of conductive lines required increases and space is wasted
Solution Approach 1:
Multiple pads within each set are merged into groups that share common routing resources. Instead of providing dedicated routing resources for each individual pad, the design combines pads into sets where first pads share first routing resources and second pads share second routing resources, significantly reducing the total routing resource count.
Solution Approach 2:
The routing resources are designed to be universal within each set - the first routing resources can serve multiple first pads, and second routing resources can serve multiple second pads. This multi-functionality allows a single routing resource to perform multiple connection functions, reducing overall resource requirements.
3Reliability
If complex interconnect structures are implemented, then electrical connections are achieved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The interconnect structure fabrication is segmented into distinct phases: forming first pads with first routing resources, and forming second pads with second routing resources. This segmentation allows each set to be manufactured independently using standardized processes, reducing overall manufacturing complexity compared to creating a single complex interconnect network.
Solution Approach 2:
Different regions of the interconnect structure are designed with different properties - first pads and their associated routing resources have one configuration, while second pads and their routing resources have another configuration. This local differentiation allows optimized manufacturing processes for each region rather than requiring a single complex process for the entire structure.
Data Source
AI summary
An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.