Grouped SAR ADC Timing for Low-Noise In-Memory Computing
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Solution Overview
Problem
In AI chips employing in-memory computing, the simultaneous operation of multiple ADCs leads to noise due to the need for sufficient reference voltage, affecting signal conversion accuracy and increasing power consumption and circuit area.
Innovation Solution
The implementation of a signal processing circuit that divides ADCs into groups and uses a time-sharing method to reduce the load on reference voltage generators, eliminating the need for simultaneous reference voltage provision across all ADCs, thereby minimizing inrush current and surge current, and utilizing a capacitor array circuit to maintain voltage levels without additional sampling switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all ADCs are enabled at the same time, then signal conversion capability is improved, but noise increases and signal conversion accuracy deteriorates
Solution Approach 1:
The patent divides multiple ADCs into distinct groups (first ADC group, second ADC group, etc.) that operate at different time periods. This segmentation allows the system to maintain multiple ADCs while preventing simultaneous operation that would cause noise interference, thus preserving signal conversion accuracy while maintaining overall conversion capability.
Solution Approach 2:
The patent implements periodic operation of ADC groups where different groups are enabled at different time periods in a cyclic manner. This periodic action ensures that reference voltage generators are not overloaded simultaneously, preventing noise generation while maintaining continuous signal conversion capability across all ADCs through time-multiplexed operation.
2Productivity
If all ADCs are enabled at the same time, then signal conversion capability is improved, but power consumption increases
Solution Approach 1:
The patent segments ADCs into multiple groups that operate at different time periods, so that reference voltage generators and associated circuitry are active only when needed for each group. This reduces the overall power consumption compared to having all ADCs and their reference voltage supplies active simultaneously, while still providing signal conversion capability for all ADCs.
Solution Approach 2:
By enabling ADC groups periodically at different time periods, the patent reduces the duty cycle of reference voltage generators and associated power-consuming components. This periodic activation reduces average power consumption while maintaining the ability to convert signals from all ADCs over time.
3Productivity
If all ADCs are enabled at the same time, then signal conversion capability is improved, but circuit area increases
Solution Approach 1:
The patent segments ADCs into multiple groups that share common reference voltage generation circuits and other support infrastructure. By operating these shared resources in time-multiplexed fashion rather than providing dedicated resources for each ADC, the patent reduces the total circuit area required while maintaining signal conversion capability for all ADCs.
Solution Approach 2:
The patent implements universal reference voltage generators and support circuits that serve multiple ADC groups at different time periods. These multi-functional components replace what would otherwise require multiple dedicated circuits, thereby reducing overall circuit area while maintaining the ability to support all ADCs for signal conversion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces noise interference, maintains signal accuracy, and decreases power consumption and circuit area by staggered operation of ADC groups and optimized voltage management.
Implementation Method 1
a capacitor array circuit, wherein a reference voltage terminal of the capacitor array circuit receives the first reference voltage... the capacitor array circuit maintains the input voltage signal during a non-reset stage
Data Source
AI summary
A signal processing circuit including a plurality of analog-to-digital conversion circuits, an in-memory computing device, and a control method thereof are provided. Each analog-to-digital conversion circuit includes a reset switch, a capacitor array circuit, a voltage comparator, and a successive approximation circuit. A first terminal of the reset switch receives a first reference voltage, and a second terminal of the reset switch receives an input voltage signal. The capacitor array circuit adjusts the input voltage signal according to a successive approximation control signal to generate an adjusted voltage. The voltage comparator compares the voltage levels of the adjusted voltage and a second reference voltage to generate a comparison signal. The successive approximation circuit generates a successive approximation control signal according to the comparison signal and generates an output digital signal corresponding to the input voltage signal. The capacitor array circuit maintains the input voltage signal during a non-reset stage.